3D Memory Channel Boosting Suppression via Select Line Voltage Control
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Solution Overview
Problem
In memory devices with a three-dimensional structure, channel boosting occurs in unselected memory blocks during a program operation in a selected memory block, leading to reliability degradation.
Innovation Solution
A memory device configuration that includes a first and second memory block, a voltage generator to apply specific voltages to global lines, and a row decoder to control pass switches, thereby suppressing channel boosting in unselected memory blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked in a three-dimensional structure, then storage density is improved, but channel boosting occurs in unselected memory blocks during program operations
Solution Approach 1:
The patent applies different voltage conditions to different spatial locations (selected vs. unselected memory blocks). Specifically, during program operations on selected blocks, unselected blocks are subjected to different voltage potentials on their select lines and bit lines, creating localized voltage conditions that prevent channel boosting in those specific regions while maintaining normal operation in selected regions.
Solution Approach 2:
The patent applies preliminary counter-voltages to unselected memory blocks before and during program operations on selected blocks. By applying specific voltages (such as 0V or negative voltages) to the select lines and bit lines of unselected blocks, the patent preemptively prevents channel boosting from occurring, countering the potential harmful effect before it can manifest.
2Shape
If poly-crystalline silicon is used for channels in stacked memory cells, then three-dimensional stacking is enabled, but grain boundaries become trap sites that increase channel potential
Solution Approach 1:
The patent changes the electrical parameters (voltage levels) applied to unselected memory blocks during program operations. By dynamically adjusting the voltage potentials on select lines, word lines, and bit lines of unselected blocks, the patent modifies the electrical conditions to prevent hole accumulation at grain boundary trap sites, thereby controlling channel potential and preventing reliability degradation.
Data Source
AI summary
Embodiments of the present disclosure relate to a memory device, and an operating method of the memory device. The memory device includes a first memory block and a second memory block each including a plurality of memory cells. The memory device also includes a voltage generator for applying operating voltages to first global lines, selectively applying a positive voltage to global select lines included in second global lines while the operating voltages are applied, and applying a ground voltage to the other global lines except the global select lines among the second global lines. The memory device further includes a row decoder for turning on first pass switches between first local lines connected to the first memory block and the first global lines, and turning off second pass switches between second local lines connected to the second memory block and the second global lines.