SRAM Keeper Circuit Shared Long-Channel NMOS Transistor
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Solution Overview
Problem
Existing SRAM technologies face challenges in maintaining stable voltage on bitlines due to leakage and noise, leading to inefficiencies in data access and requiring significant area for long-channel devices per bitline, which affects current tracking and minimum power supply voltage requirements.
Innovation Solution
A keeper circuit that includes a bias current generator and current mirror transistors, coupled with switches, maintains precharge voltages on bitlines by sharing a long-channel NMOS transistor across multiple bitlines, ensuring robust voltage maintenance and reduced area usage, while matching device characteristics to mitigate process variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a long-channel device is used per bitline to maintain stable voltage, then voltage stability is improved, but area consumption increases significantly
Solution Approach 1:
The patent combines multiple bitline keeper functions into a single shared long-channel NMOS transistor. The keeper circuit uses one long-channel device to serve multiple bitlines simultaneously, eliminating the need for separate long-channel devices per bitline. This merging approach maintains voltage stability on all served bitlines while dramatically reducing the total area required compared to having individual long-channel devices for each bitline.
2Stability of the object's composition
If traditional keeper circuits are used, then voltage maintenance is achieved, but current tracking and Vccmin performance deteriorate
Solution Approach 1:
The patent changes the channel length parameter of the NMOS transistor to create a long-channel device specifically optimized for keeper functionality. By using a longer channel length, the transistor provides better gate control and higher output impedance, which improves current tracking accuracy and lowers the minimum supply voltage (Vccmin) required for reliable operation. This parameter change enhances both voltage maintenance capability and overall circuit reliability.
3Stability of the object's composition
If multiple long-channel devices are used per bitline, then voltage stability improves, but device complexity and area increase
Solution Approach 1:
The single long-channel NMOS transistor is designed to perform multiple keeper functions simultaneously across different bitlines. This universal keeper circuit replaces what would traditionally require multiple separate long-channel devices, each dedicated to a single bitline. The multi-functional approach reduces device complexity while maintaining or improving voltage stability through the shared high-impedance current source.
Data Source
AI summary
A memory device with a keeper circuit is disclosed herein. The memory device (i) improves current tracking between the device's memory cells and the keeper circuit, (ii) improves Vccmin for memory operations, and (iii) has an efficient circuit layout. The memory device includes a memory array with a plurality of bitlines coupled to the memory cells. The keeper circuit includes a plurality of switches and a current mirror circuit. The plurality of switches is respectively coupled to the plurality of bitlines. The current mirror circuit mirrors a bias current to a plurality of current mirror transistors respectively coupled to the plurality of switches.