Memory Device External ROM Test Mode
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Solution Overview
Problem
Existing memory devices face challenges in performing various tests without increasing their size, as the number of tests increases the size of the ROM required for storing test data and algorithms.
Innovation Solution
A memory device with a first pad for receiving external ROM data and a second pad for receiving an external clock signal, along with control logic that performs operations corresponding to the external ROM data in response to the clock signal, allowing for test mode operations without increasing the device's size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of memory tests is increased, then testing capability is improved, but the size of ROM required for storing test data and algorithms increases
Solution Approach 1:
The patent extracts test data and algorithms from the internal ROM of the memory device and places them in an external memory device. The memory device receives test data from the external memory through a data input pad, eliminating the need for large internal ROM storage while maintaining comprehensive testing capability. This extraction principle directly resolves the contradiction by moving the storage burden from the memory device to an external resource.
Solution Approach 2:
The memory device is designed to perform both normal memory operations and self-test operations using a unified structure. The same data pads and control logic are used for both regular data input and test data input, eliminating the need for separate dedicated test hardware. This multi-functionality allows comprehensive testing without adding extra components that would increase device size.
2Adaptability or versatility
If dedicated test hardware is added to the memory device, then testing capability is improved, but device size and complexity increase
Solution Approach 1:
The patent designs the memory device to use its existing data input pads and control logic for both normal operations and self-test operations. The control logic receives mode selection signals to determine whether to perform normal memory operations or self-test operations, eliminating the need for separate dedicated test hardware. This approach maintains comprehensive testing capability while avoiding additional hardware that would increase device size and complexity.
Solution Approach 2:
The memory device performs self-testing using its own internal resources and externally provided test data, without requiring separate test equipment or additional dedicated test hardware. The control logic autonomously executes test algorithms based on mode selection signals, and the memory cells test themselves using the provided test data patterns. This self-service capability enables comprehensive testing while maintaining device compactness.
Data Source
AI summary
A memory device which can perform various memory tests without increasing a size of the memory device. The memory device includes: a first pad for receiving external ROM data from a memory controller; a second pad for receiving an external clock signal corresponding to the external ROM data from the memory controller; and a control logic connected to the first pad and the second pad and configured to perform an operation corresponding to the external ROM data in response to the external clock signal in a test mode.