P-Channel MOS Transistor Voltage Transfer Circuit for NAND Flash Reliability
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Solution Overview
Problem
The high voltage applied to p-type MOS transistors in NAND flash memory devices causes stress and deterioration, limiting the operational reliability of the row decoder circuit, especially as multilevel NAND flash memories require increasing voltages, making existing solutions like reducing voltage or using multiple transistors in parallel inefficient.
Innovation Solution
A semiconductor memory device with a transfer circuit comprising a p-type MOS transistor and an n-type MOS transistor, where the control circuit turns the p-type MOS transistor on and off to transfer a second voltage to the n-type MOS transistor's gate, allowing it to float and reduce stress, thereby improving operational reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If zero potential is continuously applied to the gate of the p-type MOS transistor to transfer high voltage Vpgmh, then the transistor can function as a switch for voltage transfer, but high stress is applied to the gate insulating film causing deterioration and instability
Solution Approach 1:
The patent applies periodic action by turning the p-type MOS transistor on and off in a cyclic manner during the voltage transfer process. The transistor is turned on to transfer voltage Vpgmh to the n-type MOS transistor gate, then turned off to allow the gate to float and recover. This periodic switching reduces continuous stress on the gate insulating film while maintaining voltage transfer functionality, directly resolving the contradiction between reliability and stress accumulation.
2Reliability
If multiple p-type MOS transistors are used in parallel to reduce individual transistor load, then the stress on each transistor is reduced, but the circuit size becomes very large
Solution Approach 1:
The patent applies dynamics by making the single p-type MOS transistor dynamically switch between on and off states during operation. Instead of using multiple static transistors in parallel, one transistor is dynamically controlled to perform voltage transfer intermittently. This dynamic operation reduces the continuous stress burden on the transistor while maintaining a compact circuit design, resolving the contradiction between reliability improvement and circuit size increase.
3Object-affected harmful factors
If the maximum voltage applied to the gate of the p-type MOS transistor is reduced, then stress on the transistor is reduced, but the ability to transfer high voltage Vpgm to the word line is compromised
Solution Approach 1:
The patent uses the n-type MOS transistor as an intermediary device. The p-type MOS transistor transfers voltage Vpgmh to the gate of the n-type MOS transistor, which then transfers voltage Vpgm to the word line. This intermediary arrangement allows the p-type transistor to operate at reduced voltage stress while still enabling high voltage transfer to the word line through the n-type transistor mediator, resolving the contradiction between stress reduction and voltage transfer capability.
Solution Approach 2:
The periodic switching of the p-type MOS transistor allows it to transfer high voltage Vpgmh in pulses rather than continuously. During the off period, the transistor recovers and experiences reduced stress. This periodic action maintains the ability to transfer high voltage to the word line when needed while reducing average stress on the p-type transistor, resolving the contradiction between power capability and stress reduction.
Data Source
AI summary
A semiconductor memory device includes a transfer circuit and a control circuit. The transfer circuit which includes a p-type MOS transistor with a source to which is applied a first voltage and an n-type MOS transistor to whose gate the drain of the p-type MOS transistor is connected and the first voltage is transferred, to whose source a second voltage is applied, and whose drain is connected to a load. The control circuit which turns the p-type MOS transistor on and off and which turns the p-type MOS transistor on to make the p-type MOS transistor transfer the second voltage to the load and, during the transfer, turns the p-type MOS transistor off to make the gate of the n-type MOS transistor float at the first voltage.