Data Storage Read Voltage Optimization for Error Correction
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Solution Overview
Problem
Data storage apparatuses using memory devices face issues with error bits in read data due to degraded data retention characteristics caused by neighboring memory cells, leading to increased read fail occurrences.
Innovation Solution
A data storage apparatus and operation method that perform a first read operation using an optimal read voltage, followed by an error correction code decoding operation, and a second read operation using an oversampling read voltage to detect potential error memory cells and invert bit values when neighboring memory cells are in an erased state, thereby reducing error bits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single read operation is performed using a standard read voltage, then the read operation is simple and fast, but error bits increase due to degraded data retention characteristics of read-failed memory cells
Solution Approach 1:
The read operation is divided into multiple stages: a first read operation using an optimal read voltage to initially read data from memory cells, and a second read operation using an oversampling read voltage to specifically detect and correct errors in read-failed memory cells. This segmentation allows each read stage to be optimized for its specific purpose, improving overall reliability while managing complexity through structured multi-stage processing.
Solution Approach 2:
The first read operation using the optimal read voltage is performed preliminarily to identify read-failed memory cells before performing the second read operation. This preliminary action enables the system to target only the problematic cells for correction, reducing the overall complexity compared to performing comprehensive error checking on all cells.
2Reliability
If an optimal read voltage is used to read data from memory cells, then data retention characteristics improve, but neighboring memory cells in erased state cause errors in read-failed memory cells
Solution Approach 1:
The oversampling read voltage acts as an intermediary mechanism to detect the state of neighboring memory cells that are interfering with read-failed memory cells. By using this intermediate detection step, the system can identify when neighboring erased memory cells are causing harmful interference and apply appropriate correction by inverting bit values, thus eliminating the harmful effect while maintaining the benefits of optimal read voltage.
Solution Approach 2:
The system changes the read voltage parameter between two distinct modes: the optimal read voltage for normal data reading and the oversampling read voltage for error detection in read-failed cells. This parameter change allows the system to adapt to different operational requirements - using the optimal voltage for reliable reading while using the oversampling voltage specifically to detect and correct interference from neighboring erased memory cells.
3Reliability
If multiple read operations are performed to detect and correct error bits, then the number of error bits decreases, but the read operation time increases
Solution Approach 1:
The second read operation using the oversampling read voltage is applied locally only to read-failed memory cells rather than to all memory cells in the array. This localized approach allows error detection and correction to be performed on specific problematic cells without unnecessarily extending the read time for all cells, thus reducing the time penalty associated with multiple read operations.
Solution Approach 2:
The system performs a partial second read operation only on read-failed memory cells that require correction, rather than performing complete read operations on all memory cells. This partial action approach achieves the necessary error correction while minimizing the additional time required, as the oversampling read voltage is applied selectively to only those cells where errors are detected.
Data Source
AI summary
An operation method of a data storage apparatus includes performing a first read operation using an optimal read voltage on read-failed memory cells, performing ECC decoding operation on read data, performing a second read operation using an oversampling read voltage on the read-failed memory cells when the ECC decoding operation fails, determining whether potential error memory cells which are turned on through the optimal read voltage and are turned off through the oversampling read voltage are present in the read data, determining whether neighboring memory cells which share a bit line with the potential error memory cells and are coupled to neighboring word lines are in erased state when the potential error memory cells are present, and inverting bit values corresponding to the potential error memory cells in the read data from the read-failed memory cells through the first read operation when neighboring memory cells are in erased state.