Bit Line Redundancy Repair Code Generation for NAND Flash
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Solution Overview
Problem
Existing semiconductor memory devices require a large number of fuses for bit line redundancy repair, occupying significant area and prolonging the laser repair operation time, especially in NAND flash applications with high redundancy needs.
Innovation Solution
A method and apparatus that generate a code using the states of extra fuse signals and logical addresses to select redundancy blocks, reducing the number of fuses required and enabling flexible bit line redundancy repair by matching the defective type of memory blocks, thereby minimizing fuse-occupying area and improving repair efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a large number of fuses are used for bit line redundancy repair, then the repair capability and flexibility are improved, but the area occupation increases and the laser repair operation time is prolonged
Solution Approach 1:
The patent combines multiple fuse signals into a code that selects redundancy blocks. Instead of using separate fuses for each redundancy selection, multiple fuse states are merged to form a compact code that can identify and select the appropriate redundancy block, thereby reducing the total number of fuses required while maintaining repair flexibility.
Solution Approach 2:
The fuse code serves multiple functions: it identifies defective memory blocks, selects corresponding redundancy blocks, and enables flexible repair of various defective types. A single fuse code structure is designed to handle multiple redundancy selection scenarios, making the fuse system universal rather than dedicated to specific repair cases.
2Adaptability or versatility
If a large number of fuses are used for bit line redundancy repair, then the repair capability is improved, but the laser repair operation time is prolonged
Solution Approach 1:
Multiple fuse signals are merged into a compact code structure that can be processed more quickly. By combining the information from multiple fuses into a unified code, the laser repair operation needs to process fewer discrete elements, thereby reducing the overall operation time while maintaining the same repair capability.
Solution Approach 2:
The patent changes the parameter representation from individual fuse states to a coded format. This parameter transformation allows the repair system to interpret fuse states more efficiently, reducing the time required for laser repair operations while preserving the ability to select any redundancy block.
3Reliability
If redundant cell arrays are added to replace defective memory blocks, then the reliability is improved, but the device complexity increases
Solution Approach 1:
The patent merges the redundancy selection logic into a compact code generation system that uses fuse states combined with logical address bits. This integration reduces the complexity of control circuits needed to manage redundant cell arrays, as the selection process is streamlined through code comparison rather than requiring complex decoding logic.
Solution Approach 2:
The redundancy selection circuit is designed with universal functionality that can handle various defective block types using the same code comparison mechanism. The circuit compares the generated code with stored redundancy codes to select appropriate replacement blocks, providing a unified approach that simplifies the overall device architecture while maintaining high reliability.
Data Source
AI summary
A selection method of bit line redundancy repair includes the steps of providing a plurality of logical addresses of memory blocks in the normal cell array, generating a plurality of extra fuse signals, generating a code based on states of the extra fuse signals, the code matching a defective type of the memory blocks, and selecting a plurality of redundancy blocks in the redundancy cell array to replace the memory blocks according to the code. The apparatus includes a redundancy repair enable circuit for generating a redundancy enable signal based on logical addresses of the memory blocks, a controlling fuse circuit for sending a code matching a defective type of the memory blocks, and a redundancy decoder circuit for receiving the redundancy enable signal and the code to replace a plurality of memory blocks in the normal cell array with redundancy blocks.