Adaptive Set Technique Selection for ReRAM Programming

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Resistive Random-Access Memory (ReRAM) arrays face variability in resistance values between high and low resistance states, leading to difficulties in distinguishing memory states and potential errors in reading the array, with existing programming techniques being ineffective for all memory cells.

Innovation Solution

A method involving a sequence of programming cycles with set and reset steps, where each set step uses a chosen set technique based on the lowest bit error ratio (BER) value, optimizing the application of set techniques to reduce dispersion in the low resistance state and address non-ideal cell behavior.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If full reprogramming is applied to reduce LRS variability, then manufacturing precision improves, but productivity deteriorates due to increased programming cycles

Engineering Contradiction:
ImproveLRS resistance variabilityVSAvoidprogramming speed
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent applies dynamic selection of set techniques based on real-time BER measurements. The system transitions from static full reprogramming to adaptive technique selection, choosing between different set techniques (e.g., standard set, verify set, stress set) according to the measured BER of the memory cell, thereby optimizing both precision and productivity

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of set technique selection based on BER values. By measuring BER and selecting set techniques accordingly, the system adjusts programming parameters dynamically to achieve optimal balance between LRS precision and programming speed, avoiding unnecessary full reprogramming cycles

Inventive Principle:
Principle #35Parameter changes

2Reliability

If multiple set techniques are applied to address non-ideal cell behavior, then reliability improves, but device complexity increases

Engineering Contradiction:
Improveprogramming reliabilityVSAvoidprogramming control complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements feedback control by measuring BER after programming cycles and using this information to select appropriate set techniques. The system continuously monitors memory cell performance and adjusts programming strategy accordingly, improving reliability through adaptive control while managing complexity through systematic decision-making

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent enables the memory system to self-diagnose and self-correct by measuring BER and automatically selecting appropriate set techniques. The system serves itself by identifying non-ideal cell behavior and applying corrective programming without external intervention, thereby improving reliability while keeping control logic integrated

Inventive Principle:
Principle #25Self-service

3Measurement precision

If BER-based technique selection is implemented, then measurement precision improves, but loss of time increases due to additional BER acquisition steps

Engineering Contradiction:
ImproveBER measurement accuracyVSAvoidprogramming cycle time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent performs preliminary BER measurements during manufacturing or initial characterization to establish baseline BER values for different set techniques. This preliminary action allows the system to pre-determine optimal technique selection strategies, reducing the need for extensive real-time measurements and minimizing time loss during actual programming operations

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method reduces bit-to-bit variability and improves the reliability of programming ReRAM arrays by adapting set techniques to specific memory cell behaviors, effectively narrowing the distribution of resistance values and enhancing the bit error ratio.

Implementation Method 1

The application of an electric potential difference to the two electrodes leads to the formation or the removal of an electrical connection between the two electrodes.

Methodology Applied
Scientific EffectElectrical connection formation/removal in dielectric material:

Implementation Method 2

in the case of memory cells known as OxRAM (Oxide-based RAM), a conductive filament is formed by oxygen vacancies in the dielectric material layer (here an oxide layer) separating the two electrodes.

Methodology Applied
Scientific EffectConductive filament formation by oxygen vacancies:

Implementation Method 3

in resistive random-access memories known as CBRAM (Conductive-Bridging RAM), one of the two electrodes dissolves in the dielectric material and supplies the ions forming the conductive filament.

Methodology Applied
Scientific EffectElectrode dissolution and ion transport: Electrolysis

Implementation Method 4

In ReRAM known as PCRAM (Phase-Change RAM), the two electrodes are separated by a programmable region comprising a phase-change material (PCM). This material is able to change from crystalline phase to amorphous phase upon heating.

Methodology Applied
Scientific EffectPhase change in programmable material: Phase Change

Implementation Method 5

PCRAM cells may also comprise a heater element inserted between the two electrodes and able to transform the applied voltage pulse in the heat necessary to modify the phase of the programmable region.

Methodology Applied
Scientific EffectJoule heating: Joule Heating

Data Source

PatentUS12087360B2Method for programming an array of resistive memory cells
Publication Date: 2024.09.10 WEEBIT NANO LTD
  • US12087360B2 patent drawing
  • US12087360B2 patent drawing
  • US12087360B2 patent drawing

AI summary

A method for programming at least one resistive memory cell of an array of resistive memory cells, includes a sequence of N programming cycles, N being an integer greater than or equal to 2, each programming cycle including a set procedure and a reset procedure, each set procedure including the application of a set technique chosen among a plurality of set techniques, the method including acquiring a bit error ratio value corresponding to each programming cycle for each set technique; and at each programming cycle, applying the set technique having the lowest bit error ratio value corresponding to the programming cycle.