Digital Storage TRIZ Cases
- Word Line Multiplexing in 3D Memory Arrays
Multiplexing regions utilize unused space adjacent to staircase structures, improving memory die space utilization without increasing manufacturing complexity.
- Word Driver Voltage Control for DRAM Power Reduction
Word drivers apply intermediate inactive voltages to lower current draw during refresh operations.
- SRAM Power Management Sequencing in FPGA Chips
Sequential power-on control prevents internal logic confusion and reduces power consumption by delaying SRAM activation until core voltages stabilize.
- Ferroelectric Memory Plate Power Reduction via Charge Recovery
Recycling charge from the plate line reduces power consumption in ferroelectric memory arrays while maintaining stable logic states.
- DRAM Refresh Management System for Row Hammer Mitigation
A refresh management system monitors row addresses to identify aggressor rows and selectively skip unnecessary operations.
- Superconducting Content Addressable Memory for Low Power
A content addressable memory using Josephson junctions eliminates static power dissipation by switching from DC voltage to AC current.
- Dynamic Memory Termination Impedance Switching
A memory I/O interface dynamically switches between finite termination impedance values based on rank access status.
- Decision Feedback Equalizer Non-Continuous Data Transfer Handling
A decision feedback equalizer apparatus detects end-of-transfer signals to stagger internal flip-flop bypasses during idle intervals.
- Differential Amplifier Offset Calibration for Memory Voltage Resolution
Calibration circuit adjusts internal node loading to resolve smaller differential voltages in amplifier systems.
- Oxide Semiconductor Refresh Timing Control Circuit
A refresh timing determination unit compares floating node potentials against reference levels to trigger power switches for oxide semiconductor memory cells.
- CAM Power Cut-Off Circuit for Reduced Energy Use
A power cut-off circuit isolates sense voltage from matchlines when invalid states are stored.
- Block Decoder Area Reduction via High-Voltage Switching
A block decoder uses high-voltage NMOS transistors to control signal potential levels.
- Memory Controller Differential Chip-Select Signal Termination
A memory controller generates differential chip-select signals using a predetermined resistor to absorb reflections and maintain signal integrity.
- Pipe Latch Circuit Multiplexing for Area Reduction
A pipe latch circuit uses a division unit and multiplexing unit to generate sequential control signals from source inputs.
- STT MRAM Differential Sensing via Shared Read Path
Shared read path sampling eliminates transistor mismatch errors to expand the STT MRAM read window accuracy.
- Adaptive Set Technique Selection for ReRAM Programming
A programming method selects set techniques based on bit error ratio values to reduce resistance variability in resistive memory arrays.
- Memory System Aging Compensation via Block Segmentation
A memory system maintains computation accuracy by segmenting arrays into blocks and activating backup neurons to compensate for weight drift.
- DRAM Row Control Circuit for Power-Managed Refresh
Segmented row control circuits isolate power supply periods for each memory bank, preventing voltage drops during sequential refresh cycles.