Memory Controller Differential Chip-Select Signal Termination
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Solution Overview
Problem
Conventional DDR3 SDRAM memory systems are sensitive to external environments and require costly design constraints, such as Vtt regulators, to maintain signal integrity, increasing the Bill of Material (BOM) cost and package size.
Innovation Solution
A memory controller and module that generate differential chip-select signals, using a predetermined resistor to absorb reflections and reduce signal reflections, eliminating the need for a Vtt regulator, thereby reducing BOM costs and relaxing external environment requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a Vtt regulator is used to provide predetermined voltage level at the termination of the CSN signal conducting path, then signal integrity is improved, but BOM cost increases
Solution Approach 1:
The patent extracts and removes the Vtt regulator from the memory controller design. Instead of using a dedicated voltage regulator component, the invention uses a simplified termination approach with resistors directly integrated into the signal path, eliminating the need for the separate Vtt regulator component while maintaining signal integrity.
Solution Approach 2:
The patent merges the termination function into the existing signal path by integrating resistors directly into the CSN signal conducting path. This combines multiple functions (signal termination and reflection reduction) into a single integrated solution rather than using separate dedicated components.
2Reliability
If design constraints are imposed to reduce product risks in DDR3 SDRAM interface, then signal integrity is improved, but package size and PCB area increase
Solution Approach 1:
The patent removes the requirement for extensive external termination networks and complex PCB design constraints by extracting the termination function into integrated resistors within the memory controller itself, thereby reducing the required PCB area and relaxing external design constraints.
Solution Approach 2:
The memory controller performs its own signal termination and reflection reduction internally through integrated resistors, eliminating the need for external components and complex PCB design constraints. The system serves itself by incorporating the termination function directly into the controller architecture.
3Reliability
If package and PCB design constraints are imposed to guarantee system performance, then reliability is improved, but system cost increases
Solution Approach 1:
The patent extracts the termination and reflection reduction functions from external components and design constraints, integrating them directly into the memory controller. This eliminates the need for expensive external Vtt regulators and complex PCB designs, thereby reducing system cost while maintaining reliability.
Solution Approach 2:
The memory controller independently handles signal integrity issues through internal integrated resistors, performing self-termination and self-protection against reflections without requiring external components or complex system-level design constraints, thereby reducing overall system cost.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures signal integrity and increases the speed of the chip-select signal while reducing the BOM cost by eliminating the need for a Vtt regulator, thus providing a low-cost and high-speed memory system.
Implementation Method 1
a predetermined resistor, having a first terminal coupled to a second end of the first conducting path; and a second conducting path, having a first end coupled to second pin for conducting the second signal to a second terminal of the predetermined resistor; wherein the first signal and the second signal are synchronous and configured to be a differential signal, for enabling a selected memory chip from the at least one memory chip to be accessed
Data Source
AI summary
A memory module, comprising: a first pin, arranged to receive a first signal; a second pin, arranged to receive a second signal; a first conducting path, having a first end coupled to the first pin; at least one memory chip, coupled to the first conducting path for receiving the first signal; a predetermined resistor, having a first terminal coupled to a second end of the first conducting path; and a second conducting path, having a first end coupled to second pin for conducting the second to a second terminal of the predetermined resistor; wherein the first signal and the second are synchronous and configured to be a differential signal, for enabling a selected memory chip from the at least one memory chip to be accessed.