Pipe Latch Circuit Multiplexing for Area Reduction
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Solution Overview
Problem
The increasing number of pipe latches in semiconductor memory devices leads to an undesired increase in the number and length of transmission lines, contributing to a larger peripheral area and chip size, particularly in high-speed operations and large data storage applications.
Innovation Solution
A pipe latch circuit is designed with a division unit to generate a division signal, a multiplexing unit to create pipe input control signals from a reduced number of source signals, and a pipe latch unit that sequentially latches data signals in response to these control signals, reducing the number of transmission lines and flip-flops required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of pipe latches is increased to handle larger data storage and high-speed operations, then the data processing capability is improved, but the number and length of transmission lines increase, leading to larger peripheral area and chip size
Solution Approach 1:
Multiple source signals (SRC<0:5>) are merged into a single multiplexed source signal through the multiplexing unit. The division unit generates a division signal that controls the multiplexing process, combining multiple control signals into one that drives all pipe latches sequentially. This merging approach reduces the number of transmission lines from six separate lines to a single multiplexed line, significantly decreasing the peripheral area while maintaining the ability to control multiple pipe latches for high-speed data processing
Solution Approach 2:
The patent implements dynamic time-division multiplexing where the single source signal and control signals are dynamically switched to different pipe latches based on the division signal. The control signals are generated dynamically at different time intervals, allowing the same physical transmission line to serve multiple pipe latches sequentially. This dynamic approach enables the system to maintain high data processing capability with reduced transmission line requirements
2Quantity of substance
If the number of pipe latches is increased to store more data, then the data storage capacity is improved, but the length of transmission lines increases, contributing to larger chip size
Solution Approach 1:
The patent employs periodic action through time-division multiplexing where the single control signal periodically switches to different pipe latches in a cyclic manner. The division unit generates periodic control signals that sequentially activate each pipe latch in turn. This periodic switching allows the same transmission line to service multiple pipe latches over time, enabling increased data storage capacity without proportionally increasing transmission line length, as the physical distance remains constant while the temporal distribution of control signals expands the functional capacity
3Manufacturing precision
If multiple source signals are transmitted to control multiple pipe latches, then the control precision is improved, but the number of transmission lines increases, leading to more complex peripheral area design
Solution Approach 1:
The single multiplexed source signal and control signal serve multiple functions by sequentially controlling different pipe latches. The division unit and multiplexing unit enable one control signal to perform the function of multiple separate control signals by switching its target latch based on the current time interval. This multi-functionality maintains control precision for each individual pipe latch while reducing the overall system complexity and transmission line requirements in the peripheral area design
Data Source
AI summary
A pipe latch circuit includes a division unit configured to output a division signal, a multiplexing unit configured to multiplex a plurality of source signals according to periods determined by the division signal and generate a plurality of pipe input control signals, and a pipe latch unit configured to sequentially latch a plurality of data signals in response to the pipe input control signals, wherein the source signals are sequentially activated in response to an input/output (I/O) strobe signal.