Word Line Multiplexing in 3D Memory Arrays
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Solution Overview
Problem
In three-dimensional memory arrays, the regions above the substrate adjacent to or between staircase regions are often not utilized for active circuitry, limiting the efficiency of word line multiplexing.
Innovation Solution
The implementation of circuitry for access line multiplexing, such as word line multiplexing, in regions adjacent to or between staircase regions, using a multiplexing region that includes semiconductor material portions and a gate material to modulate conductivity between these portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If regions above the substrate adjacent to or between staircase regions are left unused, then manufacturing complexity is reduced, but memory die space utilization and word line multiplexing efficiency deteriorate
Solution Approach 1:
The patent implements word line multiplexing by utilizing the vertical dimension (height direction) alongside the existing horizontal and lateral dimensions. Multiple word lines are stacked vertically and multiplexed through phase selection, transforming an otherwise unused vertical space into functional circuitry that enhances memory die space utilization without significantly increasing manufacturing complexity.
2Productivity
If word line multiplexing is implemented in unused regions, then memory die space utilization improves, but device complexity increases
Solution Approach 1:
The gate material structure serves multiple functions: it acts as a select line for enabling/disabling word line access, provides phase selection capability for multiplexing, and controls conductivity between semiconductor material portions. This multi-functionality reduces the need for separate control circuits, thereby managing device complexity while achieving improved memory die space utilization.
Solution Approach 2:
The patent utilizes conductivity modulation through voltage application to the gate material to control the electrical state of the semiconductor material portions. By changing the voltage parameter applied to the gate material, the system can switch between different operational states (conductive vs. non-conductive), enabling efficient word line multiplexing without requiring complex switching circuitry for each individual word line.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient multiplexing techniques for word lines, utilizing otherwise unused regions of the memory die, thereby enhancing the utilization of memory die space and improving memory array performance.
Implementation Method 1
a gate material portion operable to modulate a conductivity between each first portion of the plurality of first portions of the semiconductor material and a respective second portion of the plurality of second portions of semiconductor material based at least in part on a voltage of the gate material portion
Data Source
AI summary
Methods, systems, and devices for structures for word line multiplexing in three-dimensional memory arrays are described. A memory die may include circuitry for access line multiplexing in regions adjacent to or between staircase regions. For example, a multiplexing region may include, for each word line of a stack of word lines, a respective first portion of a semiconductor material and a respective second portion of the semiconductor material, and may also include a gate material operable to modulate a conductivity between the first portions and the second portions. Each word line may be coupled with the respective first portion of the semiconductor material, such that biasing of the gate material may couple the word lines with the respective second portion of the semiconductor material. Such features may support various techniques for multiplexing associated with the stack of word lines, or among multiple stacks of word lines, or both.