Superconducting Content Addressable Memory for Low Power

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Solution Overview

Problem

CMOS technology-based digital circuits face limitations in device size and power consumption, especially at high clock speeds, due to static power dissipation and current leakage even when inactive, leading to inefficiencies in high-performance digital systems.

Innovation Solution

A cache memory system utilizing a content addressable memory with Josephson magnetic random access memory (JMRAM) and superconducting quantum interference devices (SQUIDs), which uses alternating current and eliminates static power dissipation by employing Josephson junctions and SFQ pulses for data encoding and processing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If CMOS technology is used for digital circuits, then device functionality and integration are achieved, but static power dissipation and current leakage increase even when circuits are inactive

Engineering Contradiction:

Improvedevice functionalityVSAvoidstatic power dissipation

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent changes the fundamental operating parameter from DC voltage (CMOS) to AC current (superconducting), eliminating static power dissipation by using alternating current that periodically reverses direction, preventing charge accumulation and leakage

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent replaces the electronic field-based CMOS operation with a superconducting quantum interference device that uses magnetic flux and Josephson junctions, substituting the underlying physical mechanism to achieve zero static power consumption

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

2Productivity

If CMOS circuits operate at high clock speeds, then processing performance improves, but power consumption increases due to dynamic and static power loss

Engineering Contradiction:

Improveprocessing speedVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSLoss of energy

Solution Approach 1:

The patent changes the power delivery parameter from DC to AC, enabling high-speed operation without the static power penalty of CMOS. The AC current naturally supports high-frequency switching without maintaining continuous voltage levels that cause leakage

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent employs periodic AC current cycles to drive the superconducting logic circuits, using the oscillating nature of AC power to achieve high-speed switching and processing while avoiding the continuous power dissipation inherent in DC-based CMOS systems

Inventive Principle:

Principle #19Periodic action

3Stability of the object's composition

If DC voltage is used to power CMOS circuits, then stable operation is achieved, but current leakage occurs even when circuits are inactive

Engineering Contradiction:

Improveoperational stabilityVSAvoidcurrent leakage

Core Design Contradiction:

Stability of the object's compositionVSLoss of energy

Solution Approach 1:

The patent inverts the conventional approach by using AC current instead of DC voltage. This reversal eliminates the fundamental cause of leakage in CMOS, as AC current periodically reverses direction and does not maintain continuous charge flow that leads to leakage paths

Inventive Principle:

Principle #13The other way round (Inversion)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enables low-power, high-speed operations by eliminating static power dissipation and current leakage, allowing for efficient content addressable memory functions and reducing power consumption in digital systems.

Implementation Method 1

a content addressable memory using Josephson nondestructive readout (NDRO) memory cells

Methodology Applied

Scientific EffectJosephson effect: Josephson Effect

Implementation Method 2

Each of the content addressable memory elements may further include a first superconducting quantum interference device (SQUID) and a second superconducting quantum interference device (SQUID)

Methodology Applied

Scientific EffectSuperconducting quantum interference: Superconductivity

Data Source

PatentEP3446312B1Memory system with a content addressable superconducting memory

Publication Date: 2021.08.11 NORTHROP GRUMMAN SYSTEMS CORP

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AI summary

A memory system including a content addressable memory having an array of content addressable memory elements including a plurality of rows of content addressable memory elements and a plurality of columns of content addressable memory elements is provided. Each of the content addressable memory elements further includes a first superconducting quantum interference device (SQUID) and a second superconducting quantum interference device (SQUID), where an input bit to each of the content addressable memory elements is compared with: (1) a first state of the first SQUID and (2) a second state of the second SQUID to generate an output signal. The memory system further includes a Josephson magnetic random access memory (JMRAM), coupled to the content addressable memory.