Ferroelectric Memory Plate Power Reduction via Charge Recovery
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Ferroelectric memory arrays face high power consumption during access operations due to the need for varying voltages across plate lines, leading to increased energy usage and potential degradation of stored logic states in volatile memory devices.
Innovation Solution
Coupling a capacitor with a plate line in ferroelectric memory arrays allows for the reuse and supplementation of charge, reducing power consumption by minimizing the need for continuous voltage application through the use of switching components to discharge and recharge the capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If varying voltages are applied across plate lines during access operations, then read/write operations can be performed on ferroelectric memory cells, but power consumption increases
Solution Approach 1:
The patent recovers charge from the plate line after access operations by detecting when the plate line voltage returns to a threshold level, indicating that charge has been transferred to or from the ferroelectric capacitor. This recovered charge is then reused in subsequent access operations, reducing the need to continuously supply new charge from the voltage source and thereby reducing power consumption
Solution Approach 2:
The patent implements a feedback mechanism by monitoring the plate line voltage to detect when it has returned to a threshold level. This feedback signal controls switching components that manage the discharge and recharge cycles of the capacitor coupled to the plate line, enabling automated charge recovery and reuse without continuous external control
2Reliability
If continuous voltage is applied to maintain logic states in volatile memory, then data retention is improved, but power consumption increases
Solution Approach 1:
Instead of continuous voltage application, the patent uses periodic action by cycling a capacitor between charged and discharged states in synchronization with access operations. The capacitor is charged during non-access periods and discharged during access operations to provide the necessary voltage boost to the plate line, eliminating the need for continuous voltage application while maintaining the ability to perform read/write operations
Solution Approach 2:
The capacitor is automatically recharged from the voltage source when the plate line voltage returns to threshold levels, creating a self-sustaining system that recovers and reuses charge without continuous external power input. This self-service mechanism reduces power consumption while maintaining operational capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption during access operations in ferroelectric memory arrays by reusing and recycling charge, thereby minimizing energy expenditure and maintaining stable logic states in both volatile and non-volatile memory devices.
Implementation Method 1
a capacitor coupled with a plate line... By activating and deactivating one or more switching components, the voltage source may charge the capacitor. The charge of the capacitor may be subsequently discharged onto the plate line
Data Source
AI summary
Methods, systems, and devices for ferroelectric memory plate power reduction are described. A plate line may be coupled with a voltage source, a capacitor, and one or more sections of a bank of ferroelectric memory cells. During a write operation, the capacitor may be discharged onto the plate line and the resulting voltage may be adjusted (e.g., increased) by the voltage source before writing one or more memory cells. During a write-back operation, a capacitor associated with one or more memory cells may be discharged onto the plate line and stored at the capacitor. The charge may be re-applied to the plate line and adjusted (e.g., increased) by the voltage source during the write-back.