DRAM Row Control Circuit for Power-Managed Refresh
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Solution Overview
Problem
Dynamic random access memory (DRAM) semiconductor devices lose stored data over time, necessitating periodic refresh operations to prevent data loss, which can disrupt the stability of power supply voltages during active operations.
Innovation Solution
A semiconductor device with a row control circuit and row decoder that generates bank active signals and power control signals to manage the refresh operation across multiple memory banks, ensuring efficient power management and data retention by isolating power supply periods for each bank.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operations are performed periodically in DRAM devices, then data retention is maintained, but power supply voltage stability deteriorates due to voltage drops during active operations
Solution Approach 1:
The patent segments the memory system into multiple independent memory banks, each capable of being activated independently. The row control circuit generates bank active signals to selectively activate only the specific bank requiring refresh operations, while other banks remain in standby mode. This segmentation prevents simultaneous activation of all banks, thereby avoiding cumulative power consumption and voltage drops, while still maintaining data retention across all banks through periodic individual refresh cycles.
2Reliability
If all memory banks are activated simultaneously for refresh operations, then comprehensive data retention is achieved, but power consumption increases causing voltage drops
Solution Approach 1:
The memory system is divided into multiple independently controllable banks, allowing the refresh operation to be performed on one bank at a time while others remain inactive. This reduces the total power consumption during each refresh cycle compared to activating all banks simultaneously, while still achieving comprehensive data retention through sequential refresh of all banks.
Solution Approach 2:
The patent implements periodic refresh operations for each memory bank individually rather than simultaneous activation. The row control circuit generates periodic bank active signals that activate each bank in sequence at predetermined intervals. This periodic action ensures that each bank receives necessary refresh operations to maintain data retention while spreading the power consumption over time, preventing peak power demands that would cause voltage drops.
3Reliability
If refresh operations are performed frequently, then data retention reliability improves, but operational efficiency decreases due to continuous active operations
Solution Approach 1:
By segmenting the memory system into multiple banks with independent control, the patent allows refresh operations to be performed on only one bank at a time while other banks remain in low-power standby mode. This segmentation enables the system to maintain high data retention reliability through frequent refresh of individual banks without continuously activating the entire memory system, thereby preserving operational efficiency.
Solution Approach 2:
The patent implements periodic refresh operations for each bank individually, activating banks in sequence rather than continuously. The row control circuit generates periodic bank active signals that enable each bank to be refreshed at necessary intervals while remaining inactive during periods when other banks are being refreshed. This periodic action maintains data retention reliability while improving operational efficiency by reducing the time the entire memory system remains in high-power active state.
Data Source
AI summary
A device for performing a refresh operation includes a row control circuit and a row decoder. The row control circuit is configured to generate a bank active signal and a row address for controlling an active operation for a first memory bank based on a refresh signal. The row control circuit is also configured to generate the bank active signal for controlling the active operation for a second memory bank based on a power control signal. The row decoder is configured to receive the bank active signal and the row address to control the active operation for the first memory bank and the second memory bank.