Oxide Semiconductor Refresh Timing Control Circuit

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Solution Overview

Problem

Conventional semiconductor devices with silicon transistors require frequent refresh operations to maintain data retention, whereas oxide semiconductor transistors can retain data for longer periods without refresh, but efficient refresh timing determination is challenging due to unstable comparator outputs and varying manufacturing conditions.

Innovation Solution

A semiconductor device with a refresh timing determination unit, including a comparator and power management unit, that uses a reference cell and power switches to efficiently manage refresh operations by comparing detection potentials and adjusting power supply based on optimized reference potentials, thereby stabilizing refresh timing without the need for timers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Duration of action of stationary object

If conventional silicon transistor-based memory is used, then frequent refresh operations are required to maintain data retention, but this increases power consumption and operational complexity

Engineering Contradiction:
Improvedata retention timeVSAvoidpower consumption
Core Design Contradiction:
Duration of action of stationary objectVSUse of energy by moving object

Solution Approach 1:

The patent changes the material parameter of the transistor from silicon-based to oxide semiconductor, which fundamentally alters the leakage current characteristics. This material parameter change enables data retention without frequent refresh operations, thereby reducing power consumption while maintaining data integrity

Inventive Principle:
Principle #35Parameter changes

2Duration of action of stationary object

If oxide semiconductor transistors are used for long-term data retention, then refresh operations can be performed less frequently, but determining optimal refresh timing becomes challenging due to unstable comparator outputs and varying manufacturing conditions

Engineering Contradiction:
Improvedata retention timeVSAvoidrefresh timing determination stability
Core Design Contradiction:
Duration of action of stationary objectVSReliability

Solution Approach 1:

The patent employs a reference cell configured to generate a reference potential that compensates for manufacturing variations and environmental conditions. By maintaining equipotential conditions between the reference cell and memory cells, the system achieves stable refresh timing determination despite variations in oxide semiconductor characteristics across different devices and operating conditions

Inventive Principle:
Principle #12Equipotentiality

Solution Approach 2:

The patent implements a feedback mechanism where the comparator continuously monitors the potential difference between memory cells and the reference cell, and adjusts refresh timing based on this feedback. This closed-loop approach ensures reliable refresh operation by adapting to actual cell state rather than relying on fixed timing intervals

Inventive Principle:
Principle #23Feedback

3Reliability

If regular-interval refresh operation is implemented in oxide semiconductor memory, then data retention is maintained, but it is inefficient since oxide semiconductors can retain data much longer than conventional memory

Engineering Contradiction:
Improvedata retentionVSAvoidrefresh operation efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent transitions from continuous periodic refresh to event-driven periodic refresh, where refresh operations are triggered only when the comparator detects that memory cell potentials have drifted beyond acceptable thresholds. This selective periodic action maintains data retention reliability while eliminating unnecessary refresh operations, thereby improving overall system efficiency

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS9496022B2Semiconductor device including power management unit for refresh operation
Publication Date: 2016.11.15 SEMICON ENERGY LAB CO LTD
  • US9496022B2 patent drawing
  • US9496022B2 patent drawing
  • US9496022B2 patent drawing

AI summary

To provide a novel semiconductor device. The semiconductor device includes a circuit including a memory cell including a transistor using an oxide semiconductor; and a refresh timing determination unit including a capacitor, a transistor using an oxide semiconductor, and a comparator circuit. The potential of a floating node in the refresh timing determination unit is directly or indirectly input to the comparator circuit and compared with a reference potential. When the potential of the floating node becomes a certain value, a power switch operating in accordance with an output of the comparator circuit is turned on, power is supplied to the circuit including the memory cell, and then the reference potential is also changed. After that, refresh operation of the memory cell is performed. When the refresh operation is finished, the power switch is turned off.