SRAM Power Management Sequencing in FPGA Chips
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Solution Overview
Problem
In FPGA chips, the lack of standardized power-on sequences for SRAM circuits can lead to internal logic confusion and increased power consumption due to excessive SRAM voltage being powered on before core voltage is fully established.
Innovation Solution
A power management system comprising a power management circuit, controller, and oscillator that ensures the core voltage and analog input-output voltage are fully powered on before powering on and erasing SRAM circuits, using a power-on reset circuit and LDO regulators to manage voltage levels and sequences, thereby stabilizing the power supply and reducing confusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If SRAM voltage is powered on excessively fast while core voltage is powered on relatively slow, then power-on speed of SRAM is improved, but internal logic confusion occurs and power consumption increases
Solution Approach 1:
The power management circuit performs preliminary actions by first powering on the core voltage and analog input-output voltage, then subsequently powering on the SRAM voltage only after detecting that the core voltage and analog input-output voltage have stabilized. This sequential preliminary action prevents logic confusion while maintaining fast overall power-on speed.
Solution Approach 2:
The power-on reset circuit provides feedback detection to monitor the power-on status of core voltage and analog input-output voltage. This feedback mechanism triggers the SRAM voltage power-on only when the monitored voltages reach stable thresholds, ensuring logical stability while optimizing power-on speed through automated control.
2Speed
If SRAM voltage is powered on excessively fast, then power-on speed of SRAM is improved, but power consumption increases
Solution Approach 1:
The system performs preliminary power-on of core voltage and analog input-output voltage before activating SRAM voltage. This preliminary sequencing reduces instantaneous power consumption spikes by distributing the power-on load over time, while the automated control ensures the overall process remains fast.
Solution Approach 2:
The power-on reset circuit monitors voltage thresholds and provides feedback control to activate SRAM voltage only when appropriate conditions are met. This feedback-based control prevents premature SRAM power-on that would cause excessive current draw, optimizing the balance between speed and power consumption.
3Reliability
If standardized power-on sequence is implemented, then internal logic stability is improved, but power-on process complexity increases
Solution Approach 1:
The power management circuit performs self-service by automatically detecting voltage thresholds and controlling the power-on sequence without external intervention. The power-on reset circuit autonomously monitors core voltage and analog input-output voltage, then triggers SRAM voltage power-on when conditions are satisfied, simplifying the overall control architecture while ensuring standardized sequencing.
Solution Approach 2:
The power management circuit merges multiple functions into a single integrated structure: voltage monitoring, threshold detection, and sequential power-on control are combined in the power-on reset circuit. This merging reduces the need for separate control components, maintaining reliability through standardized sequencing while minimizing added complexity.
Data Source
AI summary
A power management system and method for an SRAM circuit and an FPGA chip are provided. The power management system includes a power management, a power management controller and an oscillator. The power management circuit include a power-on reset circuit used to determine whether powering-on of a core voltage and an analog input-output voltage of power supply voltages of the power management circuit is completed. The power management controller and the oscillator are used to control the power management circuit to power on the SRAM circuit after the power-on reset circuit determines that the powering-on of the core voltage and the analog input-output voltage is completed, and further used to control the power management circuit to erase the SRAM circuit after the SRAM circuit is powered on. Powering-on sequences of various internal power supplies of the FPGA chip are clear, and power consumption of the FPGA chip can be reduced.