Adaptive SoC Voltage Scaling with Fail-Safe Timing Sensing
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Solution Overview
Problem
Existing system on chip (SoC) circuits operate with unnecessary safety margins due to being designed for worst-case conditions, leading to inefficiency and potential timing failures during adaptive voltage and frequency adjustments, as the critical path replica circuit may not accurately reflect the actual margins of the SoC circuit, resulting in inadvertent failure.
Innovation Solution
Incorporating a fail-safe timing sensor within the digital domain of the SoC circuit to generate a flag signal when timing margins are violated, allowing the adaptive voltage or frequency scaling circuit to adjust the bias voltage or clock frequency accordingly, ensuring deterministic validation of critical paths and preventing failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the SoC circuit is operated with reduced voltage and/or increased frequency to recover available margins, then energy efficiency is improved, but the possibility of timing failures increases
Solution Approach 1:
The fail-safe timing sensor performs preliminary detection of timing margin violations before actual timing failures occur. By monitoring timing margins in advance and generating warning signals, the system can take preventive actions (such as adjusting voltage or frequency) before the circuit enters a failure state, thus enabling aggressive voltage/frequency scaling while maintaining reliability.
Solution Approach 2:
The timing sensor provides continuous feedback about the actual timing margins in the digital domain to the control circuit. This feedback loop enables the system to dynamically adjust operating parameters based on real-time timing margin status, allowing the SoC to operate closer to failure boundaries safely by making informed adjustments rather than using fixed conservative margins.
2Adaptability or versatility
If the critical path replica circuit is used to estimate voltage or frequency margins, then adaptive control is achieved, but inaccuracies in margin estimation occur due to variations between replica and actual circuits
Solution Approach 1:
The patent uses a critical path replica circuit as a simplified copy of the actual digital domain critical paths. While the replica cannot perfectly replicate all variations, it provides a practical approximation that enables adaptive control. The system accepts the inherent inaccuracy of the copy but compensates through conservative safety margins and continuous monitoring by the fail-safe timing sensor.
Solution Approach 2:
The fail-safe timing sensor acts as an intermediary between the replica-based estimation system and the actual digital domain. It provides an additional layer of verification that mediates between the imperfect replica measurements and the real circuit operation, generating warnings when actual timing margins approach unsafe levels despite what the replica circuit indicates.
3Reliability
If the SoC circuit is designed with worst-case process and operating conditions in mind, then reliability is ensured, but energy efficiency deteriorates due to unnecessary safety margins
Solution Approach 1:
The patent transitions from static worst-case design margins to dynamic adaptive margins. The fail-safe timing sensor continuously monitors actual timing margins, and the control circuit dynamically adjusts voltage and frequency based on real-time conditions rather than predetermined conservative values. This allows the system to operate with minimal safety margins under normal conditions while maintaining reliability through active monitoring and adjustment.
Data Source
AI summary
A system on chip (SoC) has a digital domain. An adaptive voltage/frequency scaling circuit includes a critical path replica circuit with respect to that digital domain. The critical path replica circuit generates a margin signal, and the adaptive voltage scaling circuit responds to the margin signal by decreasing bias voltage (and/or increasing clock frequency) applied to the digital domain of the system on chip so as to recover available margin. A fail-safe timing sensor is included within the digital domain of the system on chip. The timing sensor generates a flag signal when timing criteria within the digital domain are violated. The adaptive voltage scaling circuit responds to the flag signal by increasing the bias voltage (and/or decreasing the clock frequency) applied to the digital domain of the system on chip so as to implement a recovery operation.