Energy Efficient ICT TRIZ Cases

Phase-shifted periodic clock variation across processor cores reduces noise superposition and smooths power consumption without changing software.

A dual POR scheme switches between low-power and high-accuracy reset circuits to cut standby current without losing needed reset control.

Propagation-delay feedback sets the lowest passing IC supply voltage, cutting power use while preserving correct operation across process and temperature variation.

An auxiliary PLL servo loop uses a second varactor to correct slow VCO drift and temperature change while lowering phase noise and power use.

A notification signal warns the power supply before clock-driven current spikes, enabling timely voltage increases and preventing semiconductor voltage drops.

Offloading selected processes from the processor system to programmable-fabric circuits cuts execution latency and power in ICs.

Staggering channel data phases spreads switching events over time, reducing SSO noise, crosstalk, voltage noise, and peak power in memory systems.

Multi-level vector signaling cuts SSO noise and power in wide I/O memory links while preserving high throughput and low latency.

Adaptive supply modulation switches between high- and low-power amplifiers to cut low-level transmission losses and widen the power amplifier operating region.

Local cascaded BRAM routing with multiplexers and registers cuts fabric routing, lowering power while supporting higher-frequency memory access.

Separate power domains and FRAM-backed nonvolatile logic preserve state with zero leakage in sleep mode and fast wakeup restoration.

A memory DLL powers up only before active transfers and shuts down when idle, cutting clock-sync power without losing timing integrity.

DMA transfers memory descriptors to the ADC controller to sequence conversions autonomously, cutting CPU load, power use, and latency.

Measured circuit delay is used to tune supply voltage in real time, cutting power use while keeping digital timing within limits.

Dynamic over-provisioning adjusts spare capacity, ECC, and storage density to reduce wear while sustaining memory throughput and reliability.

Staggering the phase of channel groups spreads switching events in memory interfaces, reducing SSO noise and crosstalk at high data rates.

Individual clock gating lets idle pipeline modules shut off quickly while active stages keep processing, cutting power without software control.

OS tracking of active DRAM logical units enables partial refresh, cutting refresh power, heat, and unnecessary bank activity.

Selective gate sleep and early wake-up cut leakage in multi-destination logic paths without adding major timing penalties.

Keeping IC sub-units at reduced standby voltage cuts static leakage while enabling faster wake-up than full power-off.

Distributed RAID shifts striping and parity handling to autonomous storage devices, easing controller bottlenecks and improving direct data access.

Dynamic power delivery in a clock distribution network cuts skew and jitter while reducing buffer power across frequency, process, and temperature changes.

Periodic low-frequency clock switching keeps SOI buswire transistors active during idle periods, avoiding hysteresis timing penalties with low power.

Dual-switch timing prevents truncated clock pulses during source changes while preserving continuous output, phase alignment, and pulse ratio.

Distinct-band SR amplifiers with isolation stages lower UWB receiver power use and reduce injection locking and jamming.

Capacitance sensing confirms human touch on mobile hard keys, blocking accidental presses during transport or holster removal.

Local clock networks are gated on data transitions, cutting switching capacitance and dynamic power in sequential circuits.

A SoC calculates die-to-die thermal gradients and sends them to DRAM, enabling refresh-rate adjustment that prevents hotspot-driven data loss.

A fail-safe timing sensor catches margin violations in adaptive SoC voltage and frequency scaling, enabling recovery before timing failure.

Identical reference and feedback inputs let a DDR DLL hold near-lock bias during low power mode, cutting power and relocking in under 1 ns.

Capacitive pulse shaping combines delayed and inverted signals to cut inter-symbol interference and raise on-chip wire bandwidth with lower energy.

Dynamic voltage and frequency control uses shiftless interfaces to cut level shifters, power use, leakage, and area in multi-voltage circuits.

A time-based moving average delays PDM changes so inactive cores can cool active neighbors while safely shifting power for higher performance.

Multiplexed interface modules cut parallel link complexity, helping tiled processors balance reconfigurability, throughput, and power.

Dynamic mapping of object and interface circuits cuts standby hardware and processing time while preserving real-time performance.

A transmitter switches between water-filling, channel inversion, and no transmission to sustain fading links under average power limits.

An LC-tank clock generator uses frequency control and temperature compensation to keep accurate low-jitter timing while supporting power-saving modes.

Parallel delay branches with staggered taps extend HPM resolution, enabling finer AVS voltage adjustment without ultra-small delay cells.

Programmable clock drivers gate clocks within the FPGA clock tree, cutting dynamic power while freeing routing area otherwise used by enable lines.

Complementary RF inputs and full-wave rectification cut DC power draw during low-amplitude NFC carrier detection in mobile circuits.

Switching quartz oscillator supply impedance by operating mode cuts standby power while protecting timekeeping from system clock noise.

A contact sensor, latch, and switch activate bidet power only during use, cutting standby drain despite limited self-generation capacity.

Combining pre-FEC and post-FEC error metrics speeds channel estimation and improves modulation shifts under fast radio variations.

Bias control from a VCDL and timing monitor adjusts clock buffer power by frequency, process, and temperature to limit skew, jitter, and waste.

Integrated FIVR enables per-core atomic voltage and frequency changes, cutting transition delay, power waste, and stability risk.

A resynchronizing digital-to-analog RF predriver eases Class-S switching losses and distortion while extending efficient output power and carrier frequency.

Dual memory banks split cache error correction paths to protect L2 data from soft errors while limiting area and extra memory bits.

A captured reference count and low-frequency edge counter preserve accurate timekeeping through asynchronous power-saving clock switches.

A common-midpoint voltage island scheme lets registers translate logic levels directly, cutting translator power use and latency.

Dynamic clock gating disables unused retimed registers for specific opcode paths, cutting datapath power without hurting frequency.

AV Bridging carries synchronized video and audio while returning keyboard and mouse data with traffic classes and timestamps to limit LAN jitter.