Pipeline Power Gating for Multi-Destination Logic Gates
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Solution Overview
Problem
Integrated circuits face significant power consumption due to leakage current, even when idle, which is not effectively addressed by existing power-saving methods that focus on large architectural features, necessitating additional strategies to reduce power usage and heat generation, especially in battery-driven devices.
Innovation Solution
The method involves power gating, where specific groups of gates are selectively awakened or put to sleep based on clock enable signals, using control logic to manage power gates between storage elements, reducing leakage current by disconnecting idle gates from power supplies and ensuring timely wake-up of gates to minimize timing penalties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power gating is applied to gates with single destination storage elements, then leakage current is reduced, but gates with multiple destinations cannot be power gated and continue to consume leakage current
Solution Approach 1:
The patent segments the power gating control into multiple independent power gate control circuits, each associated with a specific destination storage element. Each control circuit independently manages power gating for gates that have that destination, allowing selective power gating based on individual destination activity rather than treating all gates uniformly.
Solution Approach 2:
The patent applies partial power gating by controlling different power gates independently based on the activity of individual destination storage elements. Instead of gating all gates to a destination simultaneously, only the subset of gates that actually need to drive that destination are controlled, allowing finer-grained power management.
2Loss of energy
If power gating is applied to reduce leakage current, then power consumption decreases, but timing penalties increase due to wake-up delays
Solution Approach 1:
The patent uses wake-up signals that are generated in advance of when the gates actually need to operate. The control logic detects when destination storage elements are about to become active and initiates the power gate wake-up sequence beforehand, allowing the gates to transition to active state before data needs to pass through them.
Solution Approach 2:
The patent implements dynamic power gating control where the sleep and wake states of power gates are continuously adjusted based on real-time activity detection of source and destination storage elements. The system dynamically transitions gates between power states rather than using static configurations.
3Loss of energy
If existing power saving methods reduce voltage and frequency for idle circuits, then power consumption decreases, but leakage current in small-grained features is not effectively addressed
Solution Approach 1:
The patent segments power management to the gate level rather than applying coarse-grained voltage and frequency scaling to entire circuits. Each power gate can be independently controlled based on the specific activity of its associated storage elements, enabling fine-grained power management at the smallest functional units.
Solution Approach 2:
The patent applies different power states to different gates based on their local activity requirements. Instead of uniformly reducing voltage and frequency across idle circuits, each gate receives appropriate power management based on its specific source and destination activity, allowing some gates to remain fully powered while others are gated to sleep.
Data Source
AI summary
A first and second plurality of gates are coupled respectively between first and second source storage elements and first and second destination storage elements. The first and second plurality of gates are slept to reduce leakage current in the plurality of gates under certain conditions by turning off respective one or more transistors between the first and second plurality of gates and power supplies. A third plurality of gates are maintained in a reduced leakage current state (sleep state) or regular state (wake state) based on conditions associated with the source and destination elements for the first and second plurality of gates.