Retimed Datapath Clock Gating for Unused Register Power Reduction
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Solution Overview
Problem
Conventional approaches to synthesizing register transfer level (RTL) designs are limited in achieving required speed and logic functionality while reducing power consumption, often resulting in unnecessary circuitry and increased complexity.
Innovation Solution
The method involves determining unnecessary registers in a retimed design and inserting clock gating circuitry to dynamically clock gate these registers during specific operations, thereby reducing power consumption and maintaining performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If register retiming is performed during synthesis to meet timing constraints, then timing requirements are satisfied, but unnecessary registers are added increasing power consumption
Solution Approach 1:
The patent identifies and discards unnecessary registers by analyzing which registers are not required for specific opcode combinations. Clock gating logic is then inserted to dynamically disable (gate) these unnecessary registers during their unused time periods, thereby recovering power that would otherwise be consumed by always-on register circuits.
Solution Approach 2:
The patent introduces dynamic clock gating control that adapts the operation of registers based on the current instruction being executed. The clock gating logic dynamically enables or disables clock signals to individual registers depending on whether they are needed for the current opcode combination, making the power consumption dynamic rather than static.
2Adaptability or versatility
If additional circuitry is added to meet functionality requirements, then design functionality is enhanced, but device complexity increases
Solution Approach 1:
The patent segments the clock signal distribution by introducing individual clock gating control for each register or group of registers. Instead of a single global clock control, the system divides clock management into granular per-register control, allowing independent enabling/disabling of clock signals based on specific operational needs.
Solution Approach 2:
The patent introduces clock gating logic as an intermediary component between the main clock source and the registers. This intermediary layer intelligently controls clock signal distribution based on opcode analysis, acting as a mediator that reduces unnecessary clock signal propagation to registers that don't need them for current operations.
3Speed
If conventional synthesis approaches are used to achieve required speed and logic functionality, then timing and functionality requirements are met, but power consumption remains high
Solution Approach 1:
The patent changes the operational parameter of registers from always-on to dynamically controlled by inserting clock gating logic. This parameter change allows registers to switch between enabled and disabled states based on operational requirements, directly reducing power consumption while maintaining timing performance when registers are enabled.
Data Source
AI summary
Embodiments of the invention may include receiving a design netlist representing a datapath operable to execute a function corresponding to an opcode combination. The datapath may include an input stage, a register stage, and an output stage and the register stage may include a plurality of registers. For a first function corresponding to a first opcode combination, a subset of unused registers in the plurality of registers may be automatically determined. Further, clock gating logic may be automatically inserted into the design netlist, wherein the clock gating logic is operable to dynamically clock gate the subset of unused registers contemporaneously when the datapath executes the first function corresponding to the first opcode combination.