Hierarchical Gated Clock Distribution for FPGA Power Saving
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Solution Overview
Problem
Current programmable integrated circuits, such as FPGAs and CPLDs, face challenges in reducing dynamic power consumption due to the high demand on routing area resources caused by clock enable lines, which are often unnecessary and inefficiently routed, limiting the availability of routing area for other purposes.
Innovation Solution
The implementation of a hierarchical clock distribution network with programmable clock drivers at various levels, eliminating the need for separate clock enable signals by using gated clock signals that can be dynamically enabled or disabled, thereby reducing power consumption and optimizing routing resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If clock enable lines are routed to clocked elements to save dynamic power, then power consumption is reduced, but routing area resources are heavily consumed
Solution Approach 1:
The patent merges the clock signal and clock enable function into a single gated clock signal line. Instead of routing separate clock and enable signals to each clocked element, the enable function is embedded within the clock distribution network itself through programmable clock drivers that can dynamically gate the clock signal at various hierarchy levels, thereby eliminating the need for dedicated clock enable routing resources.
Solution Approach 2:
The clock distribution network is designed to serve multiple functions: it distributes the clock signal, dynamically gates the clock signal for power saving, and provides hierarchical control. The programmable clock drivers can operate at different levels of the clock hierarchy, allowing a single network to serve both global and local clock gating needs without requiring separate dedicated enable routing infrastructure.
2Ease of operation
If separate clock enable signals are routed to each clocked element, then dynamic power can be controlled, but routing area availability for other purposes is limited
Solution Approach 1:
The patent combines power control functionality directly into the clock distribution network through programmable clock drivers. These drivers can dynamically enable or disable clock signals at different hierarchy levels based on operational needs, providing fine-grained power control without requiring separate enable signal routing to each clocked element.
Solution Approach 2:
The clock distribution network performs its own power management function through the programmable clock drivers embedded within it. The system uses its existing infrastructure (clock lines and drivers) to provide both clock distribution and power control, eliminating the need for additional dedicated enable routing resources.
3Adaptability or versatility
If clock enable lines are routed unnecessarily to some circuits, then clock gating capability is provided, but routing area is wasted
Solution Approach 1:
The patent implements dynamic clock gating through programmable clock drivers that can adaptively enable or disable clock signals based on actual operational requirements. The gating capability is not statically assigned to specific circuits but is dynamically controlled at the driver level, allowing the system to provide clock gating only where and when needed, thereby eliminating wasted routing resources.
Solution Approach 2:
The clock distribution network is segmented into a hierarchical structure with programmable clock drivers at multiple levels. This segmentation allows independent control of different clock domains and enables the system to provide clock gating capability selectively to specific regions or functions without requiring enable routing to all circuits, optimizing routing area utilization.
Data Source
AI summary
Circuits and methods for facilitating distribution of gated clocks in a programmable integrated circuit such as a field programmable gate array (FPGA) are described. Dynamic power savings are achieved in a FPGA by providing gated clock driver circuitry at various places in a hierarchical clock distribution network. The gated clock circuitry provides a clock signal gated by an enable signal to clocked elements. Configurable logic blocks (CLBs) comprising the clocked elements and programmable interconnect tiles are disposed in the gate array. Clock signals are distributed to the CLBs via a clock distribution network. Clock enable signals are provided corresponding to some of the clock signals. Clock buffers or drivers are provided within the clock distribution network that drive gated clock signals to CLBs. By disabling certain clocked elements using one or more embodiments of the invention when portions of the FPGA are inactive, dynamic power consumption is reduced.