Memory DLL Clock Gating for Low-Power High-Speed Data Transfer

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Solution Overview

Problem

High-speed data transfer in memory systems requires synchronization, but existing DLL circuits consume excessive power due to continuous operation, even during periods of non-use, which contradicts the need for reduced power consumption and increased efficiency.

Innovation Solution

Implementing a DLL circuit that switches on only during data transfer periods and utilizes a counter to delay locking until necessary, ensuring synchronization without continuous power consumption, thereby reducing power usage and maintaining data integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the DLL circuit operates continuously to maintain synchronization for high-speed data transfer, then data transfer integrity is maintained, but power consumption increases

Engineering Contradiction:

Improvedata transfer integrityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by moving object

Solution Approach 1:

The DLL circuit is activated periodically only during data transfer operations rather than continuously. The controller receives a data transfer request, activates the DLL circuit to generate synchronized clock signals, performs the data transfer, then deactivates the DLL circuit. This periodic activation pattern maintains data integrity during transfers while significantly reducing power consumption during idle periods.

Inventive Principle:

Principle #19Periodic action

Solution Approach 2:

The DLL circuit transitions between active and inactive states dynamically based on operational requirements. The system adapts the DLL's operational state - switching from a continuous operation mode to a demand-driven mode where the circuit is enabled only when data transfer is required and disabled otherwise, optimizing the balance between reliability and energy efficiency.

Inventive Principle:

Principle #15Dynamics

2Use of energy by moving object

If the DLL circuit is switched off during non-use periods, then power consumption is reduced, but synchronization capability is lost

Engineering Contradiction:

Improvepower consumptionVSAvoidsynchronization capability

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The DLL circuit is activated in advance upon receiving a data transfer request, before the actual data transfer begins. This preliminary activation ensures the DLL circuit has sufficient time to lock onto the clock signal and establish synchronization, guaranteeing that synchronized clock signals are ready and stable when data transfer commences, thus maintaining reliability while enabling power savings during idle periods.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS9047237B2Power savings apparatus and method for memory device using delay locked loop

Publication Date: 2015.06.02 INFINEON TECHNOLOGIES LLC

AI summary

Embodiments are directed to reduced power consumption for memory data transfer at high frequency through synchronized clock signaling. Delay locked loop (DLL) circuits are used to generate the synchronized clock signals. A DLL circuit consumes power as long as it is outputting the synchronized clock signals. A power saving apparatus and method are described wherein the DLL circuit is powered on when memory data access is active, while the DLL circuit is powered down when memory access is idle.