Hybrid RF Predriver Architecture for High-Power Efficient Amplification
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Solution Overview
Problem
Existing RF-PA predriver circuits face inefficiencies due to high switching frequencies and spectral distortion in Class-S digital amplifiers, and complexity in analog-based designs, which limits their ability to handle arbitrary output power levels and high carrier frequencies.
Innovation Solution
A hybrid analog/digital RF architecture with a resynchronizing digital-to-analog converter is employed, combining the integration benefits of Class-S digital designs with the extensibility of analog designs, relaxing performance requirements on output transistors and bitstream generators, and allowing for efficient high-power output stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If Class-S digital amplifiers are used with high switching frequencies, then VLSI integration benefits are achieved, but efficiency is eroded and spectral distortion is introduced
Solution Approach 1:
The patent segments the digital signal processing into two parts: a digital bitstream generator that operates at lower frequencies for VLSI integration, and an analog output stage that handles the high-frequency switching. This segmentation allows the digital portion to benefit from VLSI technology while the analog portion maintains efficiency by operating at optimal switching frequencies.
Solution Approach 2:
The patent introduces an intermediary analog buffer stage between the digital bitstream generator and the final power output stage. This intermediary converts the digital bitstream to analog form at a lower frequency, allowing the subsequent analog power stage to operate efficiently without the parasitic losses associated with high-frequency digital switching.
2Ease of manufacture
If Class-S digital amplifiers operate at super-harmonic frequencies, then integration is improved, but the technique becomes infeasible at high carrier frequencies
Solution Approach 1:
The patent employs dynamic frequency translation where the digital bitstream is generated at a base frequency suitable for VLSI integration, then dynamically upconverted to the desired carrier frequency in the analog domain. This allows the system to adapt to arbitrary carrier frequencies while maintaining the integration benefits of digital operation at lower frequencies.
Solution Approach 2:
The patent changes the operating frequency parameter from fixed super-harmonic operation to variable frequency operation. The digital bitstream generator operates at a fixed low frequency for optimal integration, while the analog stage performs frequency translation to achieve the desired carrier frequency, enabling extensibility to arbitrarily high frequencies.
3Adaptability or versatility
If analog-based RF chains are used, then extensibility to arbitrary output power levels is achieved, but design complexity increases and I/Q mismatches must be nulled
Solution Approach 1:
The patent inverts the conventional approach by generating the modulated signal digitally first, then converting to analog only at the final stage. This reversal allows digital signal processing to handle the complex modulation and frequency translation, simplifying the analog portion to basic power amplification, thereby reducing I/Q mismatch issues while maintaining power extensibility.
4Ease of manufacture
If high switching frequencies are used in Class-S amplifiers, then digital integration is improved, but output device non-idealities cause efficiency erosion
Solution Approach 1:
The patent creates a digital copy of the modulated signal at a lower frequency where VLSI technology excels, then uses this digital copy to control the analog power stage. The analog stage replicates the modulation envelope without requiring high-frequency digital switching, thereby avoiding the parasitic losses associated with high-frequency digital output device operation.
Data Source
AI summary
The invention may be embodied in radio frequency power amplifier (RF-PA) predriver circuits employing a hybrid analog/digital RF architecture including a resynchronizing digital-to-analog convertor to drive an efficient high-power output stage suitable for driving standard high power amplifier (HPA) output devices. The hybrid analog/digital RF architecture retains the advantages of high digital content integration found in conventional Class-S architecture, while relaxing the performance requirements on the output transistors and on the bitstream generator. The resulting predriver circuit combines the VLSI integration benefits of digital designs with the extensibility to arbitrary output power levels characteristic of analog designs. The hybrid analog/digital driving circuit is well suited for use with analog and Class-S HPAs used in wireless communication systems, such as the Doherty type HPA.