Parallel-Branch HPM Delay Line for Fine AVS Voltage Scaling

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Solution Overview

Problem

Conventional hardware performance monitors (HPMs) for adaptive voltage scaling (AVS) systems face limitations in resolution, particularly in making fine adjustments to supply voltage due to the constraints of delay cell minimum delays, which can hinder power-saving efficiency in systems like low-voltage applications.

Innovation Solution

The implementation of a hardware performance monitor with extended resolution, featuring a delay line with non-aligned taps in parallel branches, allowing for finer voltage adjustments by measuring delays smaller than individual delay cells, achieved through a configuration where taps in different branches have varying minimum delays, enabling more precise control over supply voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional delay cells are used in HPM, then the device structure is simple, but the measurement precision is insufficient for fine voltage adjustments

Engineering Contradiction:
Improvevoltage measurement resolutionVSAvoiddelay line structure complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The delay line is segmented into multiple parallel branches, each containing delay cells. By distributing the delay measurement across multiple branches with different tap configurations, the system achieves finer resolution without requiring individually smaller delay cells. The segmentation allows independent optimization of each branch while collectively providing extended measurement precision.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from a single-dimensional delay line to a multi-dimensional structure with parallel branches and staggered taps. This dimensional expansion allows the system to measure delays in multiple dimensions simultaneously, effectively achieving finer resolution by combining measurements from different branches rather than relying on a single linear sequence of delay cells.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Measurement precision

If delay cells with very small minimum delays are used, then the resolution is extended, but the device complexity increases significantly

Engineering Contradiction:
Improvedelay measurement resolutionVSAvoiddelay cell fabrication feasibility
Core Design Contradiction:
Measurement precisionVSEase of manufacture

Solution Approach 1:

Instead of制造单个极小延迟的延迟单元,系统将延迟测量功能分割成多个常规延迟单元,通过并行分支和交错抽头的组合配置实现等效的精细分辨率。这种方法避免了制造极端小型延迟单元的工艺困难,同时达到了延伸分辨率的目标。

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

专利通过改变延迟线的结构参数(并行分支数、抽头位置、分支间延迟差)来实现分辨率的延伸,而不是改变单个延迟单元的最小延迟参数。这种参数变化策略使得系统可以在常规制造工艺范围内实现精细测量。

Inventive Principle:
Principle #35Parameter changes

3Loss of energy

If conventional resolution HPM is used, then the device complexity is low, but the power-saving efficiency is reduced due to coarse voltage scaling

Engineering Contradiction:
Improvepower consumptionVSAvoiddelay line structure
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

专利通过编码器将并行分支的抽头采样值编码成输出代码,形成反馈机制。这种反馈机制使得AVS系统能够根据精确的延迟测量结果动态调整电压,实现更精细的功耗优化,同时编码器的设计保持了整体系统的可实现性。

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS20110291729A1Hardware performance monitor (HPM) with extended resolution for adaptive voltage scaling (AVS) systems
Publication Date: 2011.12.01 NAT SEMICON CORP
  • US20110291729A1 patent drawing
  • US20110291729A1 patent drawing
  • US20110291729A1 patent drawing

AI summary

An apparatus includes a delay line having at least two parallel branches, where each branch includes multiple delay cells coupled in series. The delay line is configured to receive an input signal and to propagate the input signal in parallel through the delay cells in the branches. The apparatus also includes multiple sampling circuits configured to sample the input signal at different taps in the branches of the delay line and to output sampled values. The taps in a first of the branches are associated with different amounts of delay compared to the taps in a second of the branches. At least some of the delay cells in the branches of the delay line could have a minimum delay, and a difference in delay between at least one tap in the first branch and at least one tap in the second branch could be less than a smallest of the minimum delays.