Low-Power DLL Weaklock Control for Fast DDR Relock
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Solution Overview
Problem
DDR interfaces consume significant power due to the long relock time of DLLs, which prevents them from being powered down during inactivity, leading to waste and increased current consumption, especially in power-down modes where exit latency is stringent.
Innovation Solution
A low power delay-locked loop (DLL) with a phase detector and controller that allows identical inputs to the reference and feedback paths during low power operation, enabling shutdown of the delay line while maintaining bias voltages close to locked values for fast relock and using a weaklock mode to reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DLLs are kept running during inactivity periods, then relock time is sufficient (100-200 ns), but power consumption increases significantly (total current about 100 mA)
Solution Approach 1:
The patent applies preliminary action by pre-maintaining the bias voltages at values close to the locked state before power-down. This preparation allows the DLL to rapidly reacquire lock after power restoration without requiring a full relock sequence, thereby resolving the contradiction between sufficient relock time and low power consumption during inactivity.
Solution Approach 2:
The patent implements dynamics by transitioning the DLL between different operational states: fully active, weak-lock (low power), and powered-down. The ability to dynamically switch states and maintain critical bias voltages during transitions enables the system to adapt power consumption to actual operational needs while ensuring rapid relock capability when needed.
2Use of energy by moving object
If DLLs are powered down to save power, then power consumption decreases, but exit latency increases beyond the 10-20 ns requirement
Solution Approach 1:
The patent applies preliminary action by pre-charging and maintaining the bias voltages at values close to the locked state before complete power-down. This preparation ensures that when power is restored, the DLL circuitry is already in a state near lock, reducing the exit latency to meet the 10-20 ns requirement while still achieving significant power savings during extended inactivity.
Solution Approach 2:
The patent applies local quality by selectively maintaining only the critical bias voltages during power-down while allowing other non-critical circuitry to be fully powered down. This selective maintenance of essential parameters enables fast relock without requiring full power to all DLL components, achieving both low power consumption and fast exit latency.
3Reliability
If DLL bandwidth is fixed for specific applications, then performance is optimized for that application, but design reuse across multiple applications with different bandwidth requirements is limited
Solution Approach 1:
The patent implements dynamics by making the DLL bandwidth programmable rather than fixed. The ability to dynamically adjust the bandwidth parameter allows the same DLL design to be optimized for different applications and bandwidth requirements, greatly enhancing design reuse while maintaining optimal performance for each specific application through programmable configuration.
Solution Approach 2:
The patent applies universality by designing the DLL with programmable bandwidth capability that allows it to serve multiple applications with different bandwidth requirements. This multi-functional design enables a single DLL implementation to be reused across various applications by simply reconfiguring the bandwidth parameter, eliminating the need for multiple specialized DLL designs.
Data Source
AI summary
A low power delay-locked loop (DLL) is presented. In one embodiment, the DLL includes a phase detector which includes a reference input and a feedback input to determine a phase difference. The DLL also includes a controller to determine whether to provide a signal to both the reference input and the feedback input such that the reference input and the feedback input receive an identical input, for example, during low power operation.