Dual-Bank Cache Hamming Code for Soft Error Correction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In digital data processors, soft errors caused by radiation can lead to corruption of data in cache memory, particularly in the level 2 cache, where static data is susceptible to errors, and existing methods for error correction are costly in terms of area and memory bits, requiring efficient implementation for high-performance devices.
Innovation Solution
A dual banking memory scheme with parity generators and detectors/correctors is employed to generate and detect errors, allowing data to be stored across multiple memory banks and corrected if necessary, optimizing error detection and correction efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complete data correction is implemented in the cache memory system, then reliability against soft errors is improved, but area and memory bit requirements increase significantly
Solution Approach 1:
The cache memory is divided into two separate banks (even bank and odd bank), with each bank handling specific address patterns. This segmentation allows independent error correction for each bank, reducing the overall complexity and area required compared to a unified correction system for the entire cache.
Solution Approach 2:
The patent introduces a bank select dimension to the memory address structure, using the least significant address bit to determine which bank to access. This dimensional change enables parallel error correction paths for different banks, improving reliability without proportionally increasing the area of individual correction circuits.
2Reliability
If complete data correction is implemented in the cache memory system, then reliability against soft errors is improved, but the number of memory bits required increases
Solution Approach 1:
By segmenting the cache into two banks with dedicated error correction circuits for each, the patent reduces the total number of correction bits needed compared to implementing full correction across a unified cache structure. Each bank requires fewer correction bits independently than a single large correction system would require.
Solution Approach 2:
The patent uses replicated error correction circuits for each bank, where identical correction logic is copied for the even bank and odd bank. This copying approach allows efficient use of standard correction cell designs, reducing the overall bit requirement compared to implementing custom correction for the entire cache.
3Productivity
If efficient error code generation and decoding is implemented, then productivity and performance are improved, but device complexity increases
Solution Approach 1:
The error generation and decoding operations are segmented into separate pathways for each bank, allowing parallel processing of error correction for even and odd addresses. This segmentation improves productivity by enabling simultaneous correction operations while keeping individual correction circuits relatively simple.
Solution Approach 2:
Error correction bits are generated and stored preliminarily during the write operation to the cache banks. This preliminary action allows the correction data to be ready when needed during read operations, improving productivity without requiring complex real-time correction circuits during data retrieval.
Data Source
AI summary
The invention is a memory system having two memory banks which can store and recall with memory error detection and correction on data of two different sizes. For writing separate parity generators form parity bits for respective memory banks. For reading separate parity detector/generators operate on data of separate memory banks.