State Transition Clock Gating for Lower Dynamic Power
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Solution Overview
Problem
Existing clock gating methods are inefficient in managing power consumption in circuit designs with sequential elements, as they often require disabling entire blocks of circuitry, leading to increased dynamic power dissipation due to higher switching capacitance in clock distribution networks.
Innovation Solution
State Transition Gating (STG) dynamically gates clock signals for groups of sequential elements based on data transitions, enabling finer granularity in power management by disabling local clock networks when data remains unchanged, using XNOR and NAND gate circuits to control clock distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional clock gating methods are used to disable entire blocks of circuitry, then power management is simplified, but dynamic power dissipation increases due to higher switching capacitance in clock distribution networks
Solution Approach 1:
The patent segments the clock distribution network into multiple independent local clock networks, each serving a specific group of sequential elements. This allows selective gating of individual local clock networks based on data transition detection, rather than gating entire blocks. The segmentation enables finer-grained power management where only the necessary portions of the clock network remain active, reducing overall switching capacitance and dynamic power dissipation while maintaining operational simplicity through modular control.
2Speed
If local clock networks are continuously enabled, then data transitions are captured without delay, but dynamic power consumption increases due to unnecessary clock network activity
Solution Approach 1:
The patent implements preliminary action by detecting data transitions in advance using detection logic that monitors input data before it reaches the sequential elements. When a data transition is detected, the system proactively enables the corresponding local clock network ahead of time, ensuring that the clock signal is ready to capture the transitioning data without delay. This preliminary detection and enablement strategy maintains fast response to data transitions while avoiding continuous clock network activity, as clocks are enabled only when and when needed.
3Loss of energy
If entire blocks of circuitry are disabled for power savings, then dynamic power dissipation is reduced, but functional granularity is lost and unnecessary functionality cannot be maintained
Solution Approach 1:
The patent applies local quality by assigning different operational states to different regions of the circuit based on their specific needs. Each local clock network and its associated sequential elements can be independently enabled or disabled based on local data transition conditions. This allows certain groups of sequential elements to remain active and responsive to data changes while other groups are gated off for power savings. The local quality approach maintains the necessary functional granularity, enabling the system to adapt to varying operational requirements across different circuit regions without losing overall adaptability.
Data Source
AI summary
In some embodiments, new clock gating approaches, referred hereafter as State Transition Gating (STG) methods and circuits are provided. In areas of circuit designs including sequential elements, the use of STG may be used to reduce dynamic power consumption.