Multi-Voltage Clock Interface Control Without Level Shifters
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Solution Overview
Problem
In mobile devices with multiple voltage domains, existing methods for reducing power consumption through voltage and frequency scaling require numerous level shifters, which occupy significant space and consume excessive power, posing challenges in managing different supply voltages and clock signals efficiently.
Innovation Solution
A system and method that utilize voltage level shiftless interface circuitries, which receive multiple supply voltages without level shifters, dynamically adjust voltage levels and clock frequencies based on estimated power consumption, leakage current, temperature, and process variations, using control units to correlate voltage and frequency across different domains, thereby reducing power consumption and leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If numerous level shifters are provided to interface multiple voltage domains, then voltage compatibility between domains is improved, but area consumption and power consumption increase significantly
Solution Approach 1:
The patent merges the voltage level shifting function with the clock signal distribution function by providing a single clock signal source that supplies clock signals to multiple voltage domains without requiring separate level shifters for each domain. This consolidation eliminates the need for numerous discrete level shifters, thereby reducing area consumption while maintaining voltage compatibility through the unified clock distribution architecture.
Solution Approach 2:
The clock signal source is designed to serve multiple voltage domains universally, providing clock signals across different voltage levels without requiring domain-specific level shifting components. This multi-functional approach allows a single component to interface with multiple voltage domains, reducing both area and power consumption compared to traditional point-to-point level shifter connections.
2Adaptability or versatility
If numerous level shifters are provided to interface multiple voltage domains, then voltage compatibility between domains is improved, but power consumption increases significantly
Solution Approach 1:
The patent merges the voltage level shifting function with the clock signal distribution function by providing a single clock signal source that supplies clock signals to multiple voltage domains without requiring separate level shifters for each domain. This consolidation eliminates the need for numerous discrete level shifters, thereby reducing area consumption while maintaining voltage compatibility through the unified clock distribution architecture.
Solution Approach 2:
The clock signal source is designed to serve multiple voltage domains universally, providing clock signals across different voltage levels without requiring domain-specific level shifting components. This multi-functional approach allows a single component to interface with multiple voltage domains, reducing both area and power consumption compared to traditional point-to-point level shifter connections.
3Use of energy by stationary object
If voltage scaling is applied to reduce power consumption, then power consumption decreases, but timing violations occur due to reduced circuit speed
Solution Approach 1:
The patent implements dynamic voltage and frequency scaling where the voltage levels and clock frequencies of different domains can be adjusted independently based on operational requirements. This dynamic control allows the system to optimize power consumption by lowering voltages in non-critical domains while maintaining higher voltages and frequencies in critical paths, thereby achieving power reduction without timing violations.
Solution Approach 2:
The system changes operational parameters (voltage levels and clock frequencies) of different voltage domains independently to balance power consumption and timing requirements. By adjusting these parameters dynamically, the system can meet timing constraints in critical paths while consuming less power in non-critical paths, resolving the contradiction between power reduction and timing compliance.
Data Source
AI summary
A system that includes a first circuitry, a second circuitry, a first supply unit and a second supply unit; characterized by including a second control unit adapted to determine a level of a second supply voltage supplied by the second supply unit in response to an estimated power consumption of the second circuitry and an estimated power consumption of a voltage level shiftless interface circuitry that receives both the first and second supply voltages. A method for controlling voltage level and clock signal frequency supplied to a system, the method includes providing a first supply voltage to a first circuitry and providing a second supply voltage to a second circuitry; characterized by determining a level of the second supply voltage in response to an estimated power consumption of the second circuitry and an estimated power consumption of a voltage level shiftless interface circuitry that receives both the first and second supply voltages.