SOI Buswire Clock Switching to Prevent Idle-State Hysteresis
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Solution Overview
Problem
In silicon on insulator (SOI) processes, components like transistors experience a timing penalty due to hysteresis effects when idle for extended periods, leading to reduced performance and requiring costly redesign or inefficient workarounds like dummy transactions to maintain functionality.
Innovation Solution
Implementing a method to alternate between primary and alternate service modes by selecting appropriate clock signals for transmission along the buswire, using a multiplexer and combinational delay buffer to prevent hysteresis, and notifying receiving devices of the operational mode to manage clock signals effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the circuit operates in primary purpose service mode only on demand with extended idle periods, then power consumption is reduced, but timing penalty occurs due to hysteresis effect on buswire
Solution Approach 1:
The patent applies periodic action by transmitting a low-frequency clock signal during idle periods to periodically activate transistors without full operational intensity. This maintains transistor switching capability and prevents hysteresis buildup while consuming minimal power compared to continuous full-frequency clocking.
Solution Approach 2:
The patent changes the clock signal frequency parameter from full operating frequency to a reduced low-frequency signal during idle periods. This parameter adjustment allows the circuit to maintain functional readiness while reducing power consumption and minimizing hysteresis effects.
2Reliability
If dummy transactions are transmitted at full normal clocking frequency during idle periods, then timing penalty is prevented, but processing performance is reduced due to delays when valid data is sent
Solution Approach 1:
Instead of continuous full-frequency dummy transactions, the patent uses periodic low-frequency clock signals during idle periods. This reduces the burden on the buswire and transistors while still preventing hysteresis, allowing valid data transactions to proceed without delay.
Solution Approach 2:
The patent applies partial action by using a reduced-frequency clock signal that provides just enough periodic activation to prevent hysteresis without the excessive action of full-frequency dummy transactions. This partial activation maintains timing performance while avoiding productivity losses.
3Loss of energy
If the circuit uses reduced frequency clock signal during idle periods, then power consumption is reduced and hysteresis is minimized, but signal transmission capability may be affected
Solution Approach 1:
The low-frequency clock signal provides periodic activation that is sufficient to maintain transistor switching capability and prevent hysteresis. While the frequency is reduced, the periodic nature ensures that transistors remain capable of rapid switching when full-speed operation is required.
Solution Approach 2:
The low-frequency clock signal performs preliminary maintenance of transistor switching capability during idle periods. This preliminary action prepares the circuit for rapid full-speed operation when needed, ensuring that signal transmission capability is preserved without continuous high-frequency signaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents timing penalties by periodically switching transistors between states, maintaining performance and allowing for optimal chip design without the need for costly redesigns or performance delays.
Implementation Method 1
a signal may not transition across a long buswire, such as a clock buswire, for an extended period of time when the circuit is not being utilized for its primary purpose. This may cause a hysteresis effect to occur on the buswire. That is, due to these extended periods of non-primary purpose use, components such as transistors that have been in one state for an extended period of time tend to favor that state
Data Source
AI summary
A method and apparatus of alternating service modes of a silicon on insulator (SOI) process circuit includes determining whether the SOI process circuit is in a first or second service mode. A first clock or a second clock is selected for transmission along a buswire of the SOI process circuit based upon the determination. A receiving device of the signal is notified whether the SOI process circuit is operating in the first service mode or the second service mode.