Clock Source Switching Circuit for Glitch-Free Phase Alignment
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Solution Overview
Problem
Existing clock multiplexer systems generate glitches when switching between clock sources, disrupting phase alignment and pulse ratio in serializer-deserializer systems, especially when one clock source is stopped during selection.
Innovation Solution
A clock-switching circuit with dual switches and control signal generation sections ensures glitch-free output by toggling enable signals before the rising edge of the lowest frequency clock, maintaining phase alignment and pulse ratio through synchronized multiplexing and delay mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a simple clock multiplexer is used to switch between clock sources, then the device complexity is reduced, but glitches are generated on the output clock line when the select line is toggled
Solution Approach 1:
The patent applies preliminary action by stopping clock two before clock one when switching, and enabling clock one after one rising and one falling edge before disabling clock two. This sequential timing ensures that the output clock signal is always a complete, non-truncated pulse from one of the input clocks, preventing glitches while maintaining a relatively simple multiplexer structure.
2Speed
If clock two is stopped when the select signal is toggled to switch to clock one, then the switching speed is improved, but the output clock signal becomes interrupted with no signal present
Solution Approach 1:
The patent implements preliminary action by stopping clock two one rising and one falling edge before the select signal toggles to select clock one. This timing ensures that clock one is already stable and ready to be selected, preventing output interruption while achieving fast switching. The enable signals are generated with precise timing relative to the select signal to ensure continuous clock output.
3Adaptability or versatility
If multiple synchronous clocks are multiplexed to support multiple data rates, then the adaptability is improved, but phase alignment and pulse ratio cannot be maintained
Solution Approach 1:
The patent uses feedback by monitoring the select signal timing and generating enable signals for clock two based on the rising and falling edges of the selected clock. This feedback mechanism ensures that when switching between clocks, the output maintains exact pulse number ratio and phase alignment, even when supporting multiple data rates. The enable signal timing is dynamically adjusted based on the select signal transitions.
Data Source
AI summary
A clock-switching circuit having at least two inputs for receiving at least two different clock sources, an output for providing a selected one of the clock sources, and a switch for selecting the one of the inputs to provide on the output, the switch including elements that, prevent the providing of a truncated version of any of the clock sources on the output, always provide a clock signal on the output, and always maintain phase alignment and pulse ratio of the clock sources on the output.