Multicore Processor Clock Phasing for Lower Radiation Noise

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Solution Overview

Problem

Multicore processors generate high-intensity radiation noise and fluctuating power consumption due to constant core frequencies, leading to increased costs and inefficiencies, especially in systems with multiple cores.

Innovation Solution

Implementing a multicore processor architecture where each core operates with a frequency that varies sinusoidally with a central frequency and a phase shift among cores, preventing noise superposition and stabilizing power consumption by shifting the phase of frequency variation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multiple cores operate at constant high frequency to increase processing capacity, then productivity is improved, but radiation noise intensity increases

Engineering Contradiction:
Improveprocessing capacityVSAvoidradiation noise
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent applies periodic action by making each core's operating frequency vary periodically over time rather than remaining constant. The frequency of each core oscillates around a central frequency, creating a time-varying operation pattern that prevents continuous high-frequency noise generation while maintaining average processing capacity.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent applies asymmetry by introducing different phase shifts for each core's frequency variation. Instead of all cores varying frequency in unison, each core has a unique phase offset, creating asymmetric frequency trajectories that prevent noise superposition and reduce overall radiation noise intensity.

Inventive Principle:
Principle #4Asymmetry

2Stability of the object's composition

If multiple cores operate at constant frequency, then processing stability is improved, but power consumption fluctuates significantly

Engineering Contradiction:
Improveprocessing stabilityVSAvoidpower consumption
Core Design Contradiction:
Stability of the object's compositionVSUse of energy by moving object

Solution Approach 1:

The patent uses periodic frequency variation to smooth power consumption. By oscillating frequencies periodically and using phase shifts, the power demand of individual cores varies in a coordinated manner that prevents simultaneous peaks, thereby stabilizing total power consumption over time.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent converts the potentially harmful effect of frequency variation (which could reduce processing stability) into a benefit. The periodic frequency changes with phase shifts actually improve power consumption stability by preventing simultaneous high-power demands, while processing stability is maintained through careful design of the frequency variation parameters.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Object-generated harmful factors

If core operating frequency is changed in time sequence to reduce noise, then radiation noise is reduced, but processing capability varies

Engineering Contradiction:
Improveradiation noiseVSAvoidprocessing capability
Core Design Contradiction:
Object-generated harmful factorsVSProductivity

Solution Approach 1:

The patent applies parameter changes by varying the operating frequency parameter of each core over time. The frequency is changed periodically around a central value, and this dynamic parameter adjustment reduces noise while the average processing capability is maintained through appropriate selection of the central frequency and variation amplitude.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9222430B2Multicore processor and onboard electronic control unit using same
Publication Date: 2015.12.29 TOYOTA JIDOSHA KK
  • US9222430B2 patent drawing
  • US9222430B2 patent drawing
  • US9222430B2 patent drawing

AI summary

A multicore processor according to the invention has a plurality of cores. The plurality of cores are configured to operate at an operation clock with a frequency varying periodically with the same period, and a variation phase of a frequency of the operation clock of each core of the plurality of cores is shifted by a predetermined amount among the plurality of cores.