Adaptive Split Addressing for Inline ECC Storage
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Solution Overview
Problem
Existing memory controllers face challenges in adapting memory transactions for inline storage configurations where sideband storage of error-checking bits is not feasible due to form factor limitations, cost constraints, or prohibitive memory technology, necessitating a solution for dynamically adapting memory transactions with adaptively split addressing for error-protected data words.
Innovation Solution
A memory controller system that employs adaptively split addressing for data and error-checking bits, using an inline storage scheme where error-checking bits are stored in a common chip with data bits, with an address translation section converting data addresses to inline data and error-checking addresses, and a command translation section generating commands for actuating data and error-checking access operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If sideband storage of ECC bits is used, then error protection reliability is improved, but device complexity and cost increase due to requiring additional dedicated storage chips
Solution Approach 1:
The patent merges the storage of data bits and ECC bits into a single memory chip by implementing inline storage configuration. The memory controller dynamically adapts addressing modes to store ECC bits within the same chip as data bits, eliminating the need for separate sideband storage chips while maintaining error protection capabilities. This is achieved through unified addressing mechanisms that can selectively access different portions of the memory space for data and ECC operations.
Solution Approach 2:
The memory chip is designed to serve multiple functions by simultaneously storing both data bits and ECC bits in an inline configuration. The same memory chip that stores data also stores error correction codes, making the storage device universal and eliminating the need for specialized sideband storage chips. The memory controller provides multi-functional addressing to accommodate both data and ECC operations within the unified chip architecture.
2Reliability
If sideband storage chips are added for ECC bits, then error checking capability is improved, but manufacturing cost increases
Solution Approach 1:
The patent combines data storage and ECC storage functions into a single memory chip to reduce manufacturing costs. By implementing inline storage where ECC bits are stored within the same chip as data bits, the system eliminates the need for additional sideband storage chips, thereby reducing component count, assembly complexity, and overall manufacturing cost while maintaining error checking capability.
3Reliability
If memory space is allocated for separate ECC storage, then error protection is improved, but memory capacity for data storage is reduced
Solution Approach 1:
The patent utilizes address space dimensionality to resolve the conflict between ECC storage and data storage capacity. By implementing inline storage with dynamic addressing modes, the system logically partitions the memory address space to accommodate both data and ECC bits within the same physical chip. The memory controller translates logical addresses to physical addresses, allowing ECC bits to occupy specific address regions without reducing the overall data storage capacity available to applications.
Data Source
AI summary
A system and method are provided for controlling access to a memory device having adaptively split addressing of error-protected data words according to an inline memory storage configuration. An address translation section executes to convert a data address associated with a received command to inline data and inline error checking addresses corresponding thereto. Each data word's data and error checking bits are stored according to respective inline data inline error checking addresses. A segment of error checking bits is thereby offset in address from at least one segment of the same data word's data bits in a common chip of the memory device. A command translation section executes to convert between a received command to data access and error checking access commands for actuating respective access operations on the memory device. An error checking storage section intermediately stores error checking bits responsive to execution of the error checking access command.