Redundant Data Error Correction TRIZ Cases
- In-Vehicle Flash Reprogramming Using Cross-Block Differential Updates
Cross-block differential reprogramming cuts update data size and restore time in in-vehicle flash memory with limited RAM.
- Redundant Analog Circuits for MOSFET Noise Self-Repair
Redundant analog elements are screened for RTN, flicker noise, and offset so only low-noise MOSFET paths remain active.
- Soft-Error Criticality Mapping for Selective IC Recovery
A criticality map links each IC storage bit to failover, reinitialization, or correction, cutting downtime from soft errors.
- Slave Register Write Verification Using Feedback Data
Feedback verification data lets a master confirm slave register writes, preventing setup errors without complex monitoring.
- Adaptive Flash Media Scan for SSD QoS Across PEC Zones
PEC-based scan periods and weak page lists let SSDs preserve QoS and data integrity without wasting scan resources over their lifespan.
- Memory ECC Layer Redistribution for Bad Column Compensation
Dynamic ECC redistribution targets bad NAND memory columns, improving data integrity, die yield, and manufacturing efficiency.
- Memory Redundant Columns for Embedded Status Storage
Redundant memory columns store operating status alongside user data, improving diagnostics without consuming dedicated storage space.
- Flash Memory Error Handling Using RAID-Scoped Data Relocation
RAID verification data limits flash error recovery to affected data only, cutting relocation time, write wear, and integrity risk.
- Configuration Register Parity Checking for Real-Time Error Detection
Real-time parity checking across configuration registers detects unintended writes and hardware faults without software overhead.
- Soft Read Threshold Selection for Error Correction and Compression
Adaptive soft read thresholds balance mutual information and compression ratio to improve memory error correction without inflating data volume.
- Memory Metadata Layout for Bounded Fault Compliance
Metadata is split across remote column planes so localized memory faults stay within one data terminal and remain correctable.
- ECC Decoder Bit-Flipping for Resistive Memory Error Correction
A detection-guided bit-flipping ECC path corrects harder memory codewords while reducing decoder area and latency in resistive and flash memories.
- Instruction Decoder Integrity Checking Using ECC-Derived Parity
ECC bits from instruction fetches are converted into byte and field parity to check decoder integrity without duplicating processor hardware.
- Memory Array Access Modes for Configurable On-Die ECC
A host-selectable ECC mode lets memory reassign array space from on-die ECC to user data or metadata for higher capacity and flexibility.
- RAID Sub-Stripe Layout With Global Parity for Flash Node Reliability
Host-managed RAID sub-stripes place multiple shards on one flash node while storing global parity elsewhere to cut writes, latency, and failures.
- Flash Memory LDPC Decoder Using Compressed Matrix Columns
By merging base-matrix columns into a smaller compressed matrix, this decoder cuts VN decoding cycles and raises NAND flash throughput.
- Memory Controller Error Correction Using Revised Likelihood Data
Stored and revised likelihood data improves non-volatile memory read error correction, helping preserve data integrity.
- CXL Memory RAID Architecture for Fault Isolation and Low Latency
RAID in CXL memory fabric isolates device faults with parity-based recovery, keeping memory access available with low latency.
- Nonvolatile Memory Read Circuit for Low-Latency Crosstalk Mitigation
Multiple reads with neighbor word-line voltage switching and one bit-line pre-charge cut crosstalk read latency while improving decode confidence.
- Randomized Parity Coding for Reliable High-Density Memory
Pseudo-random parity codes generated by an LFSR help high-density memory recover incorrect data and maintain reliable reads.
- DRAM ECC Layout Using CRC to Recover Uncorrectable Errors
A DRAM memory layout frees ECC space for CRC, then uses recalculation to locate faulty elements and recover otherwise uncorrectable errors.
- DRAM ECC Partitioning With CRC-Based Fault Location
Freed DRAM ECC space is reused for CRC, enabling fault-location checks that help correct otherwise uncorrectable memory errors.
- Virtual Disk Snapshot Migration to Hypervisor-Neutral Block Storage
A snapshot-based data mobility proxy moves virtual disk blocks to a hypervisor-neutral LUN while reducing overhead and preserving coherency.
- Memory Bad Block Handling Using Encoded Simulation Data
Encoded simulation data replaces spare units for bad block reads and writes, improving memory reliability without consuming extra space.
- Distributed Hybrid Buffer for Low-Amplification Memory Writes
A distributed buffer stores user data and parity across memory channels to cut write amplification while preserving RAS and lowering power.
- DRAM ECC Test Write Path for Parity Integrity Checking
A special DRAM ECC write mode skips parity generation so hidden ECC paths can be checked through parity comparison and syndrome correction.