CXL Memory RAID Architecture for Fault Isolation and Low Latency
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Solution Overview
Problem
Existing fabric interconnect systems lack adaptability in detecting and containing faults without requiring the whole system to shut down, and there is a need for fault-tolerant systems that maintain normal operation even when a component fails without warning, especially in memory devices with diverse types of memory attached to multiple processor nodes.
Innovation Solution
A RAID architecture is implemented in CXL devices to create redundancy in memory, allowing for prompt detection and containment of faults, supporting N+1 redundancy, single switch parity groups, and active-active redundant switches, with a fault-tolerant engine managing read/write requests and ensuring minimal latency and high throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional fault tolerance methods are used with redundancy for system components, then system reliability improves, but system complexity and cost increase significantly
Solution Approach 1:
The system divides memory into multiple banks and further segments each bank into multiple ways (e.g., 4-way segmentation). This segmentation allows independent operation of memory segments, enabling fault isolation where a failure in one segment does not affect others. The segmented architecture provides redundancy at the segment level rather than requiring complete system redundancy, reducing overall complexity while maintaining reliability.
Solution Approach 2:
Intermediary logic circuits are introduced between the processor and memory banks to handle fault detection, isolation, and remapping operations. These intermediaries manage the complexity of fault tolerance by interceptoring memory access requests, detecting failures, and redirecting accesses to healthy memory segments without requiring the entire system to shut down. This mediator layer absorbs the complexity rather than propagating it throughout the system.
2Reliability
If the system shuts down to contain faults, then system safety improves, but productivity and availability deteriorate
Solution Approach 1:
The system performs preliminary fault detection through parity checking and error correction codes (ECC) on every memory access operation. By detecting and correcting errors at the moment they occur rather than waiting for system-level diagnostics, the system can contain faults immediately at the segment level. This preliminary action prevents fault propagation that would otherwise require system-wide shutdowns, maintaining continuous operation and productivity.
Solution Approach 2:
The memory mapping is dynamically reconfigurable based on detected faults. When a memory segment is identified as faulty, the system dynamically remaps affected data to healthy segments and updates address translation tables in real-time. This dynamic adaptation allows the system to continue operating with reduced but functional capacity rather than shutting down, thereby maintaining productivity while ensuring safety by isolating faulty components.
3Reliability
If N+1 redundancy is implemented in RAID architecture, then fault tolerance improves, but device complexity and resource requirements increase
Solution Approach 1:
The system merges data storage and parity information into a unified RAID architecture where N data banks share N parity banks. This combining approach provides N+1 redundancy (N data + 1 parity per RAID group) without requiring completely separate redundant systems. The merged architecture efficiently uses memory resources by having parity information coexist with data in an organized structure, providing fault tolerance while optimizing resource utilization compared to isolated redundancy schemes.
Solution Approach 2:
Each memory bank in the RAID architecture serves multiple functions: it stores data, provides parity information for error correction, and can act as a backup for other banks. This multi-functionality means that the same physical memory resources fulfill multiple roles in the fault tolerance scheme, reducing the total quantity of memory needed compared to dedicated redundancy where separate components would be required for each function.
4Reliability
If fault detection and containment mechanisms are added, then system reliability improves, but processing latency increases
Solution Approach 1:
Fault detection operations such as parity checking and ECC are performed continuously in parallel with normal memory access operations rather than as separate sequential steps. The detection logic operates concurrently with data retrieval and storage, allowing fault identification without adding to the critical path latency. This continuous parallel operation maintains system performance while providing robust fault detection capability.
Data Source
AI summary
Systems, methods, and computer-readable storage devices can include fabric networks for isolating and correcting failures in the fabric network and device failures. The fabric network connects to a group of devices and a host. The group of devices includes at least a target data device, other data devices, and a parity device. A redundant array of independent devices (RAID) engine, which is coupled to the one group of devices, performs an access operation. The fault tolerant engine is provided in a leaf switch of the fabric network. A routing processor determines a path for a request received from the host to the target data device. The routing processor is coupled to the fault tolerant engine, and the routing processor is provided in the leaf switch.


