SoC Memory Controller Parity Block Layout for Lower Access Delay
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Solution Overview
Problem
The increase in bandwidth for memory access in system on chips (SoCs) leads to increased power consumption, necessitating more efficient bandwidth usage.
Innovation Solution
Storing data and parity together in one block within the main memory, allowing for simultaneous writing or reading via a single command, thereby reducing delay time and improving power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If data and parity are stored separately in memory, then error detection capability is maintained, but access delay increases and power consumption rises due to separate write/read commands
Solution Approach 1:
The patent merges data and parity information into a single memory block structure. Instead of storing data in one location and parity in another, both are combined in the same memory block, allowing them to be accessed simultaneously through a single command. This reduces memory access delay and eliminates the need for separate read/write operations for data and parity.
2Productivity
If bandwidth for memory access is increased to improve processing speed, then data access efficiency improves, but power consumption increases
Solution Approach 1:
By combining data and parity in the same memory block, the system can transfer both simultaneously over the memory interface using a single command. This efficient use of bandwidth transfers maximum useful information (both data and its protective parity) in each memory transaction, improving productivity without proportionally increasing power consumption.
Solution Approach 2:
The merged block structure enables continuous useful action by ensuring that every memory access operation transfers both data and parity together. This eliminates idle or partially useful transfers where only data or only parity would be accessed, maximizing the utility of each bandwidth usage event and reducing the total number of operations needed.
3Reliability
If separate commands are used for writing data and parity to memory, then data integrity can be verified, but access delay and power consumption increase
Solution Approach 1:
The patent merges data and parity into a unified memory block that is written and read as a single unit. This maintains data integrity because both data and parity are always accessed together, ensuring that parity is always available for verification. The memory controller power consumption is reduced because a single write or read command controls the entire operation rather than requiring separate commands for data and parity.
Data Source
AI summary
Provided are system on chips (SoC) and a computing devices including the SoC. The SoC may be configured to control an external main memory, and may include a memory controller configured to generate B-byte parity for A-byte data and detect an error in the A-byte data using the B-byte parity, wherein A and B are natural numbers, store the A-byte data and the B-byte parity to one memory block of the external main memory by transmitting a write command to the external main memory and the A-byte data and the B-byte parity to the external main memory and read the A-byte data and the B-byte parity from the one memory block of the external main memory by transmitting a read command to the external main memory, a data cache memory configured to transmit the A-byte data to and receive the A-byte data from the memory controller and cache the A-byte data, and a processor configured to access the external main memory.