Instruction Decoder Integrity Checking Using ECC-Derived Parity
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Solution Overview
Problem
Existing processor systems face challenges in verifying the integrity of instruction decoders without duplicating hardware, which is costly and inefficient, and traditional error detection methods are inadequate for combinational logic control functions.
Innovation Solution
A self-checking processing system uses error correction information from memory bus transactions to validate instruction decoders by converting it into byte and field parity information, allowing for integrity checking without duplicating the instruction decoder hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If lockstep configuration is used to verify processor integrity, then fault detection capability is improved, but hardware cost and die size increase due to complete duplication of processors
Solution Approach 1:
The patent creates a simplified copy of only the instruction decoder logic rather than duplicating the entire processor. The duplicate decoder receives the same instruction input and generates decoded signals that are compared with the primary decoder's output, providing fault detection without the full hardware overhead of lockstep configuration.
Solution Approach 2:
The patent segments the integrity verification process by isolating the instruction decoder as the specific component to be monitored. Instead of verifying the entire processor, only the decoder portion is duplicated and compared, reducing the verification hardware to a manageable subset of the full processor architecture.
2Ease of manufacture
If traditional error detecting code approaches like parity codes are used, then implementation simplicity is improved, but they cannot validate combinational logic control functions like instruction decoders
Solution Approach 1:
The patent introduces an intermediary comparison mechanism that bridges the primary and duplicate decoders. A comparison logic unit receives decoded signals from both decoders and determines whether they match, enabling validation of combinational logic functionality while maintaining implementation simplicity through the use of standard comparison circuits.
3Reliability
If random or asynchronous glitches affect one processor in lockstep configuration, then fault detection is triggered, but operation is halted and test procedures become complicated and time-consuming
Solution Approach 1:
The patent applies partial verification by monitoring only the decoder output signals rather than all processor outputs. This selective approach reduces false positives from random glitches and minimizes the need for extensive test procedures, as the verification is focused on the critical instruction decoding function rather than the entire processor operation.
Data Source
AI summary
A checker pipeline for checking integrity of an instruction decoder of a primary processor pipeline of a processing system including an instruction fetch checker and an instruction decoder checker. The processor pipeline includes an instruction fetch stage that receives an instruction with fields and the instruction decoder stage that decodes the instruction into instruction field values. The instruction fetch checker receives and converts instruction correction information provided with the instruction into instruction byte parity information. The instruction decoder checker includes a parity converter that converts the instruction byte parity information and instruction field information into predicted field parity information used to check the integrity of the instruction decoder. The instruction correction information is ECC bits or the like which are converted into instruction byte parity bits. The parity converter combines instruction byte parity bits with corresponding instruction bits using a logic operation into the predicted field parity information.