Multi-Level Memory ECC Sequencing for Power-Loss Data Recovery
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Solution Overview
Problem
Existing nonvolatile memory systems face data loss during momentary power failures or shutdowns when writing multi-level data, particularly in multi-level storage schemes like 4-level, 8-level, and 16-level storage, where data written to upper pages can be destroyed if the writing process is interrupted.
Innovation Solution
A memory system with a correction processing unit that performs error correction coding on lower pages before writing to upper pages, using Reed-Solomon codes and other error correction methods to ensure data integrity, even in the event of power failures, by generating error correction codes and parity data that are stored in subsequent pages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is written to upper pages before error correction is performed on lower pages, then writing speed is improved, but data integrity deteriorates due to potential loss from momentary power failures
Solution Approach 1:
The patent applies preliminary action by performing error correction coding on lower page data before writing to upper pages. The controller generates ECC codes for lower pages and writes them to designated ECC pages before proceeding with upper page writes. This ensures that if a power failure occurs during upper page writing, the lower page data remains protected and recoverable.
Solution Approach 2:
The patent segments the data writing process into distinct phases: lower page writing with immediate ECC generation, ECC code writing to separate pages, and then upper page writing. This segmentation allows error correction capabilities to be established before vulnerable upper page operations, resolving the contradiction between speed and reliability.
2Reliability
If error correction coding is performed on all lower page units before writing to upper pages, then data integrity is improved, but processing time increases
Solution Approach 1:
The patent performs error correction coding on lower pages in advance before upper page operations begin. By completing ECC generation for all lower page units beforehand and storing them in designated pages, the system ensures data integrity is established prior to vulnerable operations, while the actual upper page writing can proceed without waiting for ECC processing.
Solution Approach 2:
The patent maintains continuous useful action by overlapping operations: while ECC codes are being generated for lower pages, other system resources can be prepared for upper page writing. The process flows continuously from lower page ECC generation to upper page writing without idle waiting periods, minimizing overall processing time while ensuring integrity.
3Quantity of substance
If the number of bits to be stored increases in multi-level storage, then storage capacity is improved, but control complexity increases due to narrower threshold voltage ranges
Solution Approach 1:
The patent applies preliminary action by performing error correction coding on lower pages before upper page writing in multi-level storage systems. This pre-processing step creates a protective framework that simplifies subsequent control operations, allowing the system to handle increased storage capacity (16-level or higher) without proportionally increasing control complexity, as the ECC mechanism manages the intricacies of narrow threshold voltage ranges.
Data Source
AI summary
According to one embodiment, a memory system includes a storage unit with a plurality of pages of a plurality of nonvolatile memory cells, each page having a lower page unit and a higher page unit. A correction processing unit for correcting errors in the data stored in the storage unit on a page-by-page basis is provided. A controller is further configured to track a storage location of multi-level data in the storage unit, detect pages for which data is stored only in the lower page unit, cause the correction processing unit to generate an error correction code for the detected page units in an encoding frame, and write the error correction code to a next page unit among the plurality of pages in a set writing order after the last lower page unit in the encoding frame.