Configuration Register Parity Checking for Real-Time Error Detection
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Solution Overview
Problem
Existing data storage circuits in configuration registers are vulnerable to fatal errors due to hardware faults or unintended writes, which are not effectively detected in real time without software overhead, posing a risk to functional safety in safety-critical applications.
Innovation Solution
A data storage circuit with multiple error detection units, each connected to a configuration register, performs real-time parity checks on configuration data and parity bits, allowing automatic detection of one-bit and multiple-bit errors without software intervention, using parity generation and error correction codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional memory cell array with bit lines and word lines is used, then data can be stored in crosspoint structures, but read operations require complex sense amplifiers and write operations require multiple access transistors per cell
Solution Approach 1:
The memory array is segmented into multiple banks, with each bank containing independent bit lines and word lines. This segmentation allows parallel access to different memory regions, improving throughput while maintaining simple crosspoint cell structures. The bit lines are divided into first and second bit lines that can be independently controlled for read and write operations.
Solution Approach 2:
The access transistor serves multiple functions: it acts as a selection switch for both read and write operations, and its gate can be used to selectively connect bit lines to word lines during different operation modes. This multi-functionality reduces the number of dedicated transistors needed per cell, improving write efficiency without complicating the cell structure.
2Speed
If high-speed memory operations are implemented, then data processing speed increases, but data retention during power-off periods deteriorates
Solution Approach 1:
The memory system is divided into volatile memory cells for high-speed operations and non-volatile memory cells for data retention. This segmentation allows the system to maintain fast access speeds for active data while preserving data in the non-volatile portion during power-off periods, effectively resolving the speed-retention tradeoff.
Solution Approach 2:
A data retention circuit acts as an intermediary between the volatile memory array and external storage, maintaining copies of critical data during power transitions. This intermediary structure enables high-speed operations during powered operation while ensuring data survival through power cycles without requiring the entire memory array to be non-volatile.
3Duration of action of stationary object
If non-volatile memory cells are used for data retention, then data can be maintained during power-off, but read and write operations become complex requiring multiple transistors per cell
Solution Approach 1:
The patent merges volatile and non-volatile memory cell structures into a unified array architecture. By combining these different memory types in an integrated manner with shared bit lines and word lines, the system achieves data retention capabilities without requiring completely separate complex non-volatile memory structures, thus reducing overall device complexity while maintaining retention functionality.
Data Source
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AI summary
The invention discloses a data storage circuit comprising a plurality of configuration registers (CONFIG_REG_i) provided to store configuration data (WRDATAIN (31...0)), an error detection unit arranged to detect errors in the configuration data (WRDATAIN (31...0)) after storing configuration data (WRDATAIN (31...0)) in the respective configuration register (CONFIG_REG_i) and/or when checking the stored configuration data (WRDATAIN (31...0)) from the respective configuration register (CONFIG_REG_i). A plurality of error detection units is provided as well, wherein each configuration register (CONFIG_REG_i) is connected to a respective error detection unit to form pairs of related functional units, or wherein a set of the same bit positions in the configuration registers (CONFIG_REG_i) is connected to a respective error detection unit to form pairs of related functional units.