Randomized Parity Coding for Reliable High-Density Memory
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Solution Overview
Problem
As semiconductor memory devices increase in data transfer capacity and storage density, there is a need for effective error correction mechanisms to ensure reliable data retrieval, particularly in high-density 3D NAND memory devices where errors can occur due to manufacturing limitations and operational challenges.
Innovation Solution
A memory system incorporating a randomizer and codec to generate pseudo-randomized parity check codes using a linear feedback shift register (LFSR) to enhance data integrity, allowing for error detection and correction during read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer capacity and storage density are increased in semiconductor memory devices, then productivity and storage capacity are improved, but error occurrence rate increases due to manufacturing limitations and operational challenges
Solution Approach 1:
The patent applies preliminary action by generating parity check codes before data is written to memory. The codec generates parity check codes based on the data to be stored, and these codes are written alongside the data to the memory device. This preliminary error correction preparation enables detection and correction of errors that may occur during storage or retrieval, thus maintaining data integrity while allowing high data transfer capacity and storage density.
2Productivity
If 3D NAND memory devices are used to achieve greater storage capacity, then productivity is improved, but manufacturing precision requirements increase due to stacking multiple planes
Solution Approach 1:
The patent uses parity check codes as an intermediary mechanism to compensate for manufacturing imprecision in 3D NAND devices. The codec generates parity check codes that are stored with the data, and these codes serve as a mediator to detect and correct errors resulting from stacking variations. This allows the system to achieve high storage capacity through 3D stacking while tolerating the inherent manufacturing precision limitations.
3Reliability
If error correction mechanisms are added to ensure reliable data retrieval, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements error correction by changing the parameter of data representation through the addition of parity check codes. Instead of modifying the core memory cell structure or adding complex correction circuits, the system changes the data parameters by appending calculated parity information. This approach improves data retrieval reliability while minimizing increases in device complexity, as the parity generation and verification can be performed through simple logical operations.
Data Source
AI summary
Aspects of the disclosure provide a memory system. For example, the memory system can include a memory device configured to store data and one or more parity check codes. The memory system can further include a randomizer configured to generate a sequence of pseudo-randomized numbers using a randomizer seed in response to a clock signal according to a predetermined rule. The memory system can further include a codec coupled to the memory device and the randomizer. The codec can be configured to generate the one or more parity check codes according to the pseudo-randomized numbers and the data. The parity check codes are to be written to the memory device when a write operation is performed and to be used to recover at least one of the data stored in the memory device when a read operation is performed and the at least one of the data is incorrect.