Flash Memory LDPC Decoder Using Compressed Matrix Columns
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Solution Overview
Problem
Conventional LDPC decoders for NAND flash memory require numerous decoding cycles due to calculations on every column of the base matrix, leading to time consumption and efficiency reduction, especially with large matrix sizes.
Innovation Solution
A flash memory controller and method that transforms the base matrix into a compressed matrix with fewer columns by grouping elements, reducing the number of VN unit decoding cycles per iteration through a grouping strategy and column-sum calculation circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the VN unit conducts calculations on every column of the base matrix during each iteration, then the decoding accuracy is maintained, but the decoding cycle count increases and throughput decreases
Solution Approach 1:
The patent merges multiple columns of the base matrix into a compressed matrix with fewer columns. Columns that share the same variable node connections are combined into single columns, reducing the total number of columns from M to S (where S < M). This merging maintains the essential decoding relationships while reducing the computational cycles required per iteration, thereby improving throughput without sacrificing decoding accuracy.
Solution Approach 2:
The compressed matrix columns serve multiple functions: each column represents multiple original base matrix columns and maintains the parity-check relationships for the associated variable nodes. The grouping strategy ensures that each column in the compressed matrix can be processed to update V2C messages for multiple original columns simultaneously, making the decoding process more efficient while preserving the necessary error correction capabilities.
2Reliability
If the base matrix size is increased to improve error correction capability, then the reliability improves, but the decoding cycle count increases due to more columns
Solution Approach 1:
The patent applies column merging to large base matrices by grouping columns that share the same variable node connection patterns. This reduces the number of columns that need to be processed individually during each iteration, thereby reducing decoding time while maintaining the error correction capability provided by the larger matrix structure. The compressed matrix preserves the essential parity-check relationships needed for error correction.
Solution Approach 2:
The patent changes the structural parameter of the base matrix by transforming it into a compressed matrix with fewer columns. This parameter change (from M columns to S columns) reduces the iteration complexity and decoding time while maintaining the code's error correction capability through the preserved parity-check relationships in the compressed structure.
Data Source
AI summary
A flash memory controller and a flash memory access method are provided. The flash memory controller comprises a decoder. The decoder is configured to perform a decoding operation based on a N×M base matrix of a LDPC code to decode the read information from a flash memory. The decoder comprises a controller, a variable node (VN) unit, and a check node (CN) unit. The controller is configured to transform the base matrix into a compressed matrix of size N×S, where S is smaller than M. The VN unit and the CN unit are configured to perform message updates between variable nodes and check nodes to generate decoding results that converge to a codeword. During each decoding cycle, the VN unit performs calculations on each column of the compressed matrix.