DRAM ECC Test Write Path for Parity Integrity Checking
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Solution Overview
Problem
Existing DRAM ECC circuits are not adequately tested, leading to incomplete error coverage and potential integrity issues, as current solutions fail to test all ECC paths and do not provide data patterns for parity check bits.
Innovation Solution
Implement a special write feature in the ECC test mode that allows writing data without parity calculations, enabling comprehensive testing of ECC circuit paths by comparing parity bits of corrected and uncorrected data to generate syndromes for error detection and correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ECC testing methods are used, then testing process is simple, but error coverage is incomplete and integrity is compromised
Solution Approach 1:
The testing process is divided into multiple phases: initial write phase with parity calculation, special write phase without parity calculation, and read verification phase. This segmentation allows comprehensive testing of ECC paths by comparing results between phases, resolving the contradiction between simple testing and complete error coverage.
Solution Approach 2:
The patent performs preliminary actions by writing data with parity calculations first, then writing the same data without parity calculations. This preliminary setup creates the conditions necessary for comprehensive ECC path testing, enabling detection of errors that would otherwise remain undetected.
2Reliability
If all ECC paths are tested, then integrity is improved, but data patterns for parity check bits are not provided
Solution Approach 1:
The patent uses feedback by comparing the read data from the special write phase (without parity) against the expected values. The syndrome calculation provides feedback information about ECC path integrity, enabling detection of errors while maintaining complete data pattern information through the comparison process.
3Reliability
If ECC circuits are not adequately tested, then device complexity is reduced, but error detection capability is insufficient
Solution Approach 1:
The special write feature serves multiple functions: it writes data without parity calculations for testing purposes, enables comprehensive ECC path testing, and maintains compatibility with normal read operations. This multi-functionality improves error detection capability without significantly increasing device complexity.
Data Source
AI summary
Implementations herein describe a system including a system-on-chip including at least a host and a dynamic random-access memory (DRAM) in communication with the SoC, the DRAM including at least an error correction code engine, the system configured to allow the host to write first data to the DRAM, calculate parity bits for the first write data, store the first write data and the parity bits in a DRAM core of the DRAM, allow the host to write second data to the DRAM, store the second write data in the DRAM core without calculating parity bits for the second write data, enable the DRAM to calculate parity bits of the second write data and compare the parity bits of the second write data to the parity bits of the first write data, and calculate a syndrome based on a comparison to correct errors detected in the DRAM core.