Nonvolatile Memory Read Circuit for Low-Latency Crosstalk Mitigation
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Solution Overview
Problem
Nonvolatile memory systems suffer from crosstalk interference, leading to errors in data read operations, which existing methods to mitigate crosstalk are complex and time-consuming, limiting reading throughput.
Innovation Solution
A storage system with circuitry that reads a target word line multiple times at different voltages and neighbor line settings, producing multiple binary readouts and confidence levels, processed by combinational logic to enhance decoding capabilities, while minimizing pre-charge operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing methods are used to mitigate crosstalk among memory cells, then crosstalk errors are reduced, but reading throughput is limited due to complex and time-consuming processes
Solution Approach 1:
The system pre-charges bit lines before reading operations and uses predefined full conducting voltage or partial conducting voltage for non-target word lines to proactively mitigate crosstalk effects before they degrade read accuracy
Solution Approach 2:
The system dynamically adjusts read voltage levels and non-target word line voltage settings (full conducting vs. partial conducting) based on detected crosstalk conditions, changing operational parameters to optimize both accuracy and speed
2Measurement precision
If multiple read operations are performed to mitigate crosstalk, then decoding accuracy is improved, but latency in read operations increases
Solution Approach 1:
The system performs multiple read operations continuously on the same bit lines without discharging and re-precharging between reads, maintaining continuous useful action to reduce latency while gathering multiple measurements for improved decoding accuracy
Solution Approach 2:
The system performs a fixed number of read operations (e.g., two reads) to obtain sufficient confidence levels for decoding, avoiding excessive reads that would unnecessarily increase latency while ensuring adequate accuracy through the predetermined read count
3Reliability
If pre-charge operations are performed frequently to mitigate crosstalk, then read accuracy is maintained, but processing time increases
Solution Approach 1:
Bit lines are pre-charged once before a sequence of read operations, and this pre-charge state is maintained throughout multiple reads, avoiding the need to repeatedly pre-charge and thereby reducing processing time while maintaining accuracy
Data Source
AI summary
A storage system includes circuitry and memory cells that are coupled to multiple WLs and to multiple BLs. The circuitry includes combinational logic, and is configured to: set a read voltage to a target WL, and set each of the other WLs, including a neighbor WL neighboring to the target WL, to a predefined full conducting voltage or to a predefined partial conducting voltage lower than the full conducting voltage, pre-charge the BLs, and while discharging the BLs, read a page from a group of target memory cells multiple times, to produce multiple respective binary readouts, at least one of the readouts corresponds to setting the neighbor WL to the partial conducting voltage, apply the combinational logic to the readouts to produce (i) output bits of the page, and (ii) confidence levels associated with the output bits, and transmit the output bits and the confidence levels to a controller.