DRAM ECC Partitioning With CRC-Based Fault Location
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current error correction codes (ECC) in DRAM devices are limited in their ability to correct uncorrectable errors, as they require significant memory space for ECC information, reducing the available storage capacity and failing to correct errors beyond a certain threshold.
Innovation Solution
A memory device configuration that allocates a portion of memory elements for data, another for ECC information, and a third for error correction code (CRC), allowing for reduced ECC information storage while maintaining error detection and correction capabilities by recalculating CRC to identify and correct errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If more ECC symbols are stored in DRAM device, then error correction capability is improved, but available storage capacity is reduced
Solution Approach 1:
The patent segments the memory device into distinct portions: a first portion for storing data values, a second portion for storing ECC information, and a third portion for storing error detection codes. This segmentation allows optimized allocation of memory resources, where the ECC portion is sized specifically for correction needs rather than consuming excessive capacity, and the error detection code portion enables additional validation without requiring full ECC redundancy for all data.
2Reliability
If conventional ECC symbols are used, then up to N/2 symbol errors can be corrected, but inability to correct more errors limits reliability
Solution Approach 1:
The patent merges multiple error handling mechanisms into a unified system: conventional ECC correction for up to N/2 errors is combined with error detection codes for identifying additional errors. This hybrid approach allows the system to detect and handle more error types (including uncorrectable errors) while maintaining the mathematical simplicity of traditional ECC algorithms, avoiding the need for complex alternative schemes.
3Quantity of substance
If DRAM device capacity is increased, then more data can be stored, but proportion of memory used for ECC remains significant
Solution Approach 1:
The patent changes the parameters of the error protection scheme by introducing a separate error detection code portion with different sizing considerations than traditional ECC. The error detection code can be configured with varying lengths independent of the ECC symbol count, allowing optimization of the ratio between protection overhead and data capacity. This parameter flexibility enables scaling the solution to match different capacity requirements while maintaining adequate error protection levels.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
The technology is directed to error detection and correction in a memory device containing dynamic random-access memory (DRAM) elements. The DRAM elements are configured to store data in a first number of elements, store error correction code (ECC) information in a second number of elements and storing an error correction code in a third number of elements. The amount of memory allocated to ECC is reduced without adversely affecting the ECC capability by storing an error correction code, such as a cyclic redundancy code (CRC) in the freed-up memory space. A location of an uncorrectable error is identified assuming one of the elements contains an error then recalculating the selected data using the ECC, recalculating the CRC and comparing it to the original CRC. A match indicates the faulty value has been found and corrected. A mismatch indicates that the selected element is not the location of the error.