Flash Memory Data Recovery via Dynamic Read Voltage Adjustment

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Solution Overview

Problem

Flash memory systems face challenges in data recovery due to high original error rates exceeding the error correction ability of Error Correcting Codes (ECC), especially when data retention noise causes threshold voltage distribution shifts, leading to bit error rates beyond ECC correction capabilities.

Innovation Solution

A data recovery method that dynamically adjusts the read voltage by calculating a check node error rate and adjusting the read voltage step size, repeatedly reading data until the minimum check node error rate is achieved, using a functional relationship between bit error rates and read voltage adjustments based on threshold voltage distribution states.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a preset read voltage is used to read data from flash memory, then the read operation is simple and fast, but the bit error rate exceeds the error correction ability of ECC when data retention noise causes threshold voltage distribution shifts

Engineering Contradiction:
Improvedata recovery accuracyVSAvoidread voltage adjustment process
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a feedback mechanism by calculating the check node error rate based on read data and using it to dynamically adjust the read voltage. The controller monitors the error rate and modifies the read voltage accordingly, creating a closed-loop system that adapts to changing threshold voltage distributions caused by data retention noise, thereby maintaining data recovery accuracy without requiring manual intervention

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent transforms the static read voltage approach into a dynamic one by continuously adjusting the read voltage based on real-time error rate calculations. The read voltage is no longer fixed but adapts dynamically to the current state of the flash memory, allowing the system to respond to threshold voltage shifts and maintain optimal reading conditions throughout the data retention period

Inventive Principle:
Principle #15Dynamics

2Reliability

If the read voltage is adjusted dynamically based on check node error rate, then data recovery accuracy is improved, but the time required to find optimal read voltage increases

Engineering Contradiction:
Improveerror correction capabilityVSAvoidvoltage adjustment iteration time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies partial action by adjusting the read voltage in controlled steps rather than exhaustively searching all possible voltage values. The adjustment step size is optimized to reach the optimal voltage point efficiently, performing only the necessary adjustments to achieve error correction capability without unnecessary iterations, thus balancing accuracy improvement with time consumption

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent changes the read voltage parameter dynamically based on the calculated check node error rate. By modifying this critical parameter in response to measured performance metrics, the system adapts to threshold voltage distribution shifts and improves error correction capability. The parameter adjustment follows an optimized trajectory that reduces the number of iterations needed to reach the optimal state

Inventive Principle:
Principle #35Parameter changes

3Reliability

If error correction code is used to ensure consistency between written and read data, then data reliability is improved, but high original error rates exceed the error correction range of ECC

Engineering Contradiction:
Improvedata consistencyVSAvoiderror rate detection accuracy
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The patent performs preliminary action by adjusting the read voltage before the ECC correction process. By optimizing the read voltage in advance based on the check node error rate, the system reduces the original error rate to within the ECC correction capability range, ensuring that the subsequent ECC process can effectively correct remaining errors and maintain data consistency

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12197282B2Data recovery method for flash memory
Publication Date: 2025.01.14 INST OF MICROELECTRONICS CHINESE ACAD OF SCI LTD
  • US12197282B2 patent drawing
  • US12197282B2 patent drawing
  • US12197282B2 patent drawing

AI summary

A data recovery method for a flash memory includes: reading data from the flash memory by using preset read voltage; calculating a check node error rate corresponding to the data; calculating a read voltage adjustment step size according to the check node error rate; adjusting the preset read voltage according to the read voltage adjustment step size and reading data from the flash memory by using the adjusted preset read voltage, and repeating the operation of calculating a check node error rate corresponding to the data to operation of adjusting the preset read voltage according to the read voltage adjustment step size and reading data from the flash memory by using the adjusted preset read voltage, until the check node error rate is minimum; and selecting a read voltage corresponding to the minimum check node error rate to read data from the flash memory, so as to perform data recovery.