Dual-NVM Memory Controller for MCU Data Error Recovery
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Solution Overview
Problem
The evolution of embedded non-volatile memory (e.g., eFlash) has lagged behind the advancement of microcontroller unit (MCU) process platforms, and new NVM technologies like RRAM face reliability issues due to environmental susceptibility and exceed conventional error correction capabilities, leading to data integrity challenges.
Innovation Solution
A memory controller architecture incorporating a first NVM with faster speeds and a second NVM for backup, coupled with memory controllers for read/write control and content transfer, enabling error correction and backup content retrieval to ensure data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If new NVM (e.g., RRAM) is used to replace eFlash memory, then read and write speed is improved, but data reliability deteriorates due to environmental susceptibility
Solution Approach 1:
The patent creates a backup copy of data from the first NVM (fast but unreliable) to the second NVM (slow but reliable). The second NVM serves as a backup storage that preserves data integrity, allowing the system to retrieve correct backup content when errors occur in the primary storage, thus resolving the reliability issue while maintaining speed benefits.
Solution Approach 2:
The patent changes the reliability parameter by introducing a second NVM with different characteristics (higher reliability, lower speed) to complement the first NVM. By adjusting the system's storage architecture to include both types of memory with different parameter profiles, the system achieves both speed and reliability requirements.
2Reliability
If conventional ECC function is used for error correction, then data correctness is improved for single-bit errors, but error correction capability is limited and cannot handle errors exceeding ECC capacity
Solution Approach 1:
The patent performs preliminary action by pre-storing backup content in the second NVM before errors occur. When errors exceed ECC correction capability, the system can retrieve the pre-stored backup content to repair the data, providing adaptability beyond conventional ECC limits without requiring real-time complex error analysis.
Solution Approach 2:
The second NVM acts as an intermediary between the corrupted data in the first NVM and the repair process. Instead of relying solely on ECC algorithms, the backup NVM provides a mediator source of correct data that can be used to repair errors beyond ECC capability, enhancing the system's error handling versatility.
3Adaptability or versatility
If backup content is stored in a separate NVM for error repair, then data repair capability is improved, but device complexity increases
Solution Approach 1:
The second NVM is designed with multi-functionality, serving both as a backup storage for reliability and as a repair source for error correction. This universal component handles multiple tasks (backup, error recovery, data preservation) without requiring separate dedicated systems for each function, thereby limiting the increase in device complexity.
4Productivity
If fast NVM is used as main memory, then system performance is improved, but data integrity deteriorates due to susceptibility to environmental factors
Solution Approach 1:
The patent segments the storage system into two distinct parts: the first NVM for performance-critical operations and the second NVM for reliability-critical backup functions. This segmentation allows each component to optimize for its specific role without compromising the other, maintaining system performance while ensuring data integrity through the reliable backup storage.
Data Source
AI summary
A memory controller and an MCU chip are provided by the present application. The memory controller adds a second memory controller to conventional memory controller architecture and is coupled to second NVM storing a backup of content of first NVM in the memory controller. With this arrangement, one more memory access path is established, which takes full advantage of the fast reading characteristics of the first NVM, and once a system bus identifies an error in content read from the first NVM or a problematic address, the second memory controller can automatically read exactly corresponding backup content from the second NVM and provide it on the system bus, or use it to accurately correct the error in the first NVM. This ensures correctness of content that a central processing unit (CPU) or other master on the system bus reads, without interrupting execution of the system's program.