Memory Sub-Array Layout for Parallel ECC and Meta Data Handling
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently storing meta data and generating parity data, leading to increased latency due to the need for separate processing of normal and meta data, which affects the refresh operations as memory capacity increases.
Innovation Solution
A semiconductor memory device architecture that includes a memory cell array with sub-array blocks and separate error correction code (ECC) engines for normal and meta data, allowing for parallel processing and reduced latency by storing meta data in adjacent regions and generating parity data separately for both types of data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If meta data is stored separately from normal data in existing semiconductor memory devices, then storage organization is simplified, but latency increases due to separate processing requirements
Solution Approach 1:
The memory device is divided into multiple sub-array blocks, each containing both normal data storage regions and meta data storage regions. This segmentation allows parallel processing of normal data and meta data within the same physical block, reducing latency while maintaining organized storage structure.
Solution Approach 2:
The patent merges the storage of normal data and meta data into the same sub-array blocks, allowing them to be processed simultaneously. The column access circuit is designed to handle both data types within the same block structure, eliminating the need for separate processing paths and reducing overall latency.
2Productivity
If a single ECC engine processes both normal data and meta data, then device complexity is reduced, but processing speed decreases due to sequential operations
Solution Approach 1:
The ECC processing function is segmented into a main ECC engine for normal data and separate sub-ECC engines for meta data. Each sub-ECC engine operates independently within its designated sub-array block, enabling parallel error correction processing and increasing overall productivity.
Solution Approach 2:
Instead of using a single ECC engine that must process all data sequentially, the patent employs multiple partial ECC engines (one for normal data, separate sub-ECC engines for meta data). This excessive distribution of processing functions enables simultaneous operation and improves throughput despite increased device complexity.
3Quantity of substance
If memory capacity increases to meet storage demands, then storage capability improves, but refresh operation performance deteriorates due to increased latency
Solution Approach 1:
The memory device is divided into multiple sub-array blocks with dedicated meta data storage regions. This segmentation enables the refresh control circuit to manage refresh operations more efficiently by processing normal data and meta data in parallel across different blocks, maintaining refresh performance even as total memory capacity increases.
Data Source
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AI summary
A semiconductor memory device includes a memory cell array and a column access circuit. The memory cell array includes a plurality of sub-array blocks and each of the sub-array blocks includes volatile memory cells. The column access circuit receives a plurality of data units, each of which includes normal data and meta data having a ratio of k:1, which is associated with managing the normal data, allocates p column selection lines associated with transferring the data units to the bit-lines to a plurality of normal data and a plurality of meta data in the data units with the ratio of k:1, and stores a sub unit of a first normal data among the plurality of normal data and a sub unit of a first meta data in a first region and a second region of a first sub-array block of the plurality of sub-array blocks, respectively.