Memory Address Remapping for Defective Hardware Locations
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Solution Overview
Problem
Existing memory page offline features in operating systems require more memory space to be offlined than is actually affected by bad memory locations, necessitating complex software intervention and tracking, which can lead to inefficiencies and downtime.
Innovation Solution
A hardware-assisted memory page offline mechanism using hashing engines to dynamically map and remap memory addresses, masking and shifting affected areas to maintain system stability and performance without extensive software intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software-based memory page offline mechanism is used to handle bad memory locations, then system stability is maintained, but excessive memory space must be offlined (more than actually affected) and complex software tracking is required
Solution Approach 1:
The patent introduces a hardware intermediary (address remapping circuit or hashing engine) that sits between the memory controller and the defective memory locations. This hardware component automatically remaps addresses to avoid bad locations without requiring software intervention, thus maintaining system stability while eliminating complex software tracking requirements.
Solution Approach 2:
The patent replaces the software-based memory management mechanism with a hardware-based address remapping mechanism. This substitution eliminates the need for software to track and manage offline pages, reducing software complexity while maintaining the reliability benefit of avoiding bad memory locations.
2Reliability
If software-based memory page offline mechanism is used to handle bad memory locations, then system stability is maintained, but memory allocation efficiency decreases due to excessive deallocation
Solution Approach 1:
The patent applies address remapping only at the specific defective memory locations rather than offlining entire memory pages or sections. This localized approach preserves the quality and usability of healthy memory regions while selectively avoiding only the bad locations, thereby maintaining memory allocation efficiency while ensuring system stability.
Solution Approach 2:
The patent dynamically changes the address mapping parameters through hardware remapping when defective locations are detected. This allows the system to adaptively adjust memory addressing without requiring software to reconfigure memory management, maintaining both stability and allocation efficiency.
3Productivity
If hardware address remapping is implemented to avoid bad memory locations, then memory allocation efficiency is improved, but device complexity increases due to additional hardware components
Solution Approach 1:
The patent designs the address remapping hardware to serve multiple functions: it not only avoids defective memory locations but also maintains address translation, supports memory virtualization, and works across different memory types. This multi-functionality justifies the added hardware complexity by providing broad system benefits beyond simple defect avoidance.
Solution Approach 2:
The patent implements a dynamic address remapping mechanism that can be configured and updated at runtime based on detected defective locations. This dynamic capability allows the hardware to adapt to different memory failure scenarios without requiring physical reconfiguration, balancing hardware complexity with operational flexibility and efficiency.
Data Source
AI summary
Provided is an apparatus, a device, a method, a computer program, and a non-transitory, computer-readable medium comprising a program code for a computer system, as well as a computer system. An apparatus (10) for a computer system (100) comprises memory circuitry (11) for storing information identifying at least one defective memory hardware location, and one or more hardware address determination circuitries (12, 13) configured to determine a mapping between a physical memory address and a hardware location address of corresponding memory (101, 102), wherein the one or more hardware address determination circuitries are configured to adapt the mapping at run-time upon obtaining updated information identifying at least one defective memory hardware location.