Memory Read Control Using Soft-Bit Compression and LDPC Recovery
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Solution Overview
Problem
Downgraded flash memory dies in memory devices exhibit unstable characteristics, leading to data errors and reduced performance, and existing solutions introduce additional issues.
Innovation Solution
A method and apparatus that includes a memory controller with LDPC code decoding and error recovery circuits to perform read optimization, utilizing compression and soft decoding to ensure error-free data reading, even with downgraded flash memory dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If downgraded flash memory dies are used to reduce costs, then manufacturing cost is reduced, but data stability and reliability deteriorate
Solution Approach 1:
The patent changes the parameter of soft bit precision by implementing compression that converts multiple soft bits into fewer compressed soft bits, while maintaining adequate error correction capability. This allows using downgraded memory dies with lower inherent quality while still achieving reliable data recovery through optimized error correction parameters
Solution Approach 2:
The patent extracts only the essential error correction information by compressing soft bits to retain the most significant reliability data while discarding redundant information. This extraction approach maintains data stability with downgraded dies by focusing on critical error correction parameters rather than processing all raw soft bit data
2Quantity of substance
If compression operation is performed to reduce soft bit count, then memory buffer size is reduced, but decoding accuracy may deteriorate
Solution Approach 1:
The patent changes the parameter of soft bit representation by implementing a compression scheme that maps multiple soft bits to fewer compressed soft bits using optimized mapping functions. This parameter transformation reduces memory buffer requirements while preserving sufficient decoding accuracy for error correction
Solution Approach 2:
The patent applies partial compression by retaining the most significant soft bit information while compressing less critical data. This partial action approach maintains adequate decoding accuracy for error correction while achieving substantial memory buffer size reduction
Data Source
AI summary
A method for performing data access control of a memory device includes: receiving a plurality of host commands from a host device for performing data access upon a non-volatile (NV) memory according to the plurality of host commands, wherein the data access includes data reading; and performing a read optimization procedure for maintaining correctness of the data reading, for example: performing reading operation to obtain multiple channel values; performing compression operation to convert multiple first soft bits in any channel value into multiple second soft bits, to generate a compressed channel value for being buffered in volatile memory; reading multiple compressed channel values from the volatile memory; and utilizing a low-density parity-check (LDPC) code decoding engine circuit to perform LDPC code decoding according to the multiple compressed channel values, and utilizing an error recovery circuit to perform error recovery operation according to the multiple channel values, to generate error-free data.