Soft-Error Criticality Mapping for Selective IC Recovery
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Solution Overview
Problem
Soft errors in integrated circuits cause persistent corruption and prolonged downtime, exceeding permitted downtime in high-availability applications like telecommunications, as existing methods for error detection and correction are inefficient and time-consuming.
Innovation Solution
A programmable integrated circuit with a triply-redundant soft-error management circuit that includes a check circuit, classification circuit, and correction circuit, using error detection codes to repeatedly check for soft errors, classify their criticality, and initiate appropriate mitigative techniques such as failover, reinitialization, or correction based on specified criticality classes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the integrated circuit is reset to correct soft errors, then the soft error is corrected, but the system downtime increases significantly
Solution Approach 1:
The configuration memory is divided into multiple banks, and the soft error management is segmented into different criticality classes. When a soft error is detected, only the specific bank or circuit affected is reset or reconfigured, rather than resetting the entire integrated circuit. This segmentation allows selective recovery of affected components while maintaining operation of unaffected components, thereby reducing overall system downtime.
Solution Approach 2:
The system dynamically selects the appropriate mitigative technique based on the criticality class of the corrupted storage bit. The soft error management circuit adapts its response in real-time: for non-critical errors, it applies lighter mitigative actions (such as reinitialization); for critical errors, it applies stronger actions (such as full reset). This dynamic adaptation optimizes the balance between error correction effectiveness and downtime minimization.
2Reliability
If a full system reset is performed to correct soft errors, then all soft errors are corrected, but the productivity decreases due to prolonged downtime
Solution Approach 1:
Different mitigative techniques are applied to different criticality classes of storage bits based on their local importance to system operation. Non-critical storage bits receive lighter treatment (reinitialization), while critical storage bits receive more thorough treatment (reset or reconfiguration). This localized quality approach ensures that error correction is tailored to the specific needs of each storage bit, maintaining overall system productivity while ensuring necessary correction.
Solution Approach 2:
The system changes the parameter of mitigative technique intensity based on the criticality class parameter of the corrupted storage bit. By adjusting the severity of the corrective action according to the criticality parameter, the system achieves effective error correction for critical bits while minimizing disruption to non-critical operations, thereby maintaining higher overall productivity and system availability.
3Adaptability or versatility
If multiple mitigative techniques are available for soft error correction, then the adaptability improves, but the device complexity increases
Solution Approach 1:
The system performs preliminary classification of storage bits into criticality classes before soft errors occur. The map specifying criticality classes is pre-established, and the soft error management circuit is pre-configured with multiple mitigative techniques. When a soft error is detected, the system simply looks up the pre-determined criticality class and applies the corresponding pre-planned mitigative technique, avoiding the need for complex real-time decision-making and reducing operational complexity.
Solution Approach 2:
The map specifying criticality classes acts as an intermediary between the error detection circuit and the multiple mitigative techniques. Instead of the complex circuit directly managing all possible mitigative techniques, the map serves as a simplified interface that translates error locations into appropriate corrective actions. This intermediary structure reduces the complexity of the soft error management circuit by providing a clear, lookup-based decision mechanism.
Data Source
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AI summary
Methods and systems mitigate a soft error in an integrated circuit (200, 302). A map (350, 352) is stored (112) that specifies a criticality class for each storage bit (332, 334) in the integrated circuit. A mitigation technique is associated with each criticality class. The soft error is detected (114) in a corrupted one of the storage bits. The mitigation technique is performed (116) that is associated with the criticality class specified in the map for the corrupted storage bit.