ECC Decoder Bit-Flipping for Resistive Memory Error Correction
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Solution Overview
Problem
Existing error correction methods for resistive and flash memories face challenges with high latency and surface area costs due to the use of powerful error-correcting codes, particularly in scenarios with high error rates.
Innovation Solution
An ECC decoder is implemented with a detection module to identify up to r-1 erroneous bits and a correction module to correct them, followed by iterative decoding cycles with single-bit inversion to reduce the number of errors, optimizing for smaller footprint and reduced latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If powerful error correcting codes are used to correct high error rates, then error correction capability is improved, but latency and area overhead increase significantly
Solution Approach 1:
The patent segments the error correction task into two distinct modules: a correction module that handles up to r-1 erroneous bits using traditional ECC decoding, and a detection module that identifies when exactly r erroneous bits are present. This segmentation allows the system to use simpler, faster correction logic for the majority case while only invoking complex procedures when necessary, thereby reducing average latency and area overhead.
Solution Approach 2:
The patent applies partial action by designing the correction module to handle only up to r-1 errors directly, rather than attempting to correct all r errors in a single complex operation. When r errors are detected, the system performs a secondary operation (flipping one bit) to reduce the error count to r-1, then applies correction. This partial approach breaks down a complex r-error correction problem into simpler sub-problems.
2Reliability
If the ECC decoder is designed to correct up to r erroneous bits directly, then error correction capability is improved, but functional complexity and hardware resources increase
Solution Approach 1:
The patent divides the ECC decoder into functionally distinct segments: a correction module optimized for correcting up to r-1 errors with low complexity logic, and a detection module that monitors syndrome patterns to identify when exactly r errors are present. This functional segmentation allows each module to be optimized independently, reducing overall complexity compared to a monolithic r-error correction design.
Solution Approach 2:
The patent introduces an intermediary detection mechanism that acts as a mediator between the received codeword and the correction module. The detection module analyzes syndrome values to determine whether exactly r errors are present, and if so, triggers a bit-flipping operation that transforms the problem into one solvable by the simpler correction module. This intermediary detection layer reduces the complexity burden on the core correction logic.
3Device complexity
If traditional ECC decoding is used without error detection, then implementation is simpler, but latency increases due to unnecessary complex decoding operations
Solution Approach 1:
The patent performs preliminary error detection before committing to full correction decoding. The detection module quickly evaluates syndrome patterns to determine whether exactly r errors are present, allowing the system to take preliminary action (either proceed directly to simple correction or invoke the bit-flipping sequence) before engaging complex decoding operations. This preliminary detection prevents unnecessary execution of complex latency-inducing procedures.
Solution Approach 2:
The patent implements dynamic operation modes in the ECC decoder: a fast correction mode for the common case of fewer than r errors, and a secondary detection-and-flip mode triggered only when exactly r errors are detected. The system dynamically selects the appropriate operation path based on real-time syndrome analysis, optimizing latency by avoiding complex operations when they are not needed while maintaining the ability to handle worst-case scenarios.
Data Source
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AI summary
The invention relates to a device and a method for error correction in resistive memories or flash memories, protected by an error correcting code which allows the correction of at least two erroneous bits per code word stored in memory. The device combines a correction module capable of correcting up to r-1 erroneous bits per code word, and a detection module for checking the number of erroneous bits per code word. The detection module is arranged to detect whether the read code word comprises at most r-1 erroneous bits, and if not, to initiate a sequence of decoding operations on a succession of words each of which comprises a single bit inverted with respect to the read code word. A check is then made to verify whether the number of erroneous bits in the version of the code word with inversion of one bit has become correctable. As soon as this condition is satisfied, the code word can be corrected.